Recent developments and challenges in FPGA-based time-to-digital converters
Over the past few years, the gap between field-programmable gate array (FPGA) and
application-specific integrated circuit (ASIC) performance levels has been narrowed due to …
application-specific integrated circuit (ASIC) performance levels has been narrowed due to …
Time-to-digital converter IP-core for FPGA at state of the art
F Garzetti, N Corna, N Lusardi, A Geraci - IEEE Access, 2021 - ieeexplore.ieee.org
The Field Programmable Gate Array (FPGA) structure poses several constraints that make
the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits …
the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits …
Development and initial results of a brain PET insert for simultaneous 7-Tesla PET/MRI using an FPGA-only signal digitization method
In study, we developed a positron emission tomography (PET) insert for simultaneous brain
imaging within 7-Tesla (7T) magnetic resonance (MR) imaging scanners. The PET insert …
imaging within 7-Tesla (7T) magnetic resonance (MR) imaging scanners. The PET insert …
From multiphase to novel single-phase multichannel shift-clock fast counter time-to-digital converter
N Lusardi, F Garzetti, A Costa… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
With countless applications, time measurements are among industrial electronics' current
most important challenges. This is not a matter of precision, which by now standard …
most important challenges. This is not a matter of precision, which by now standard …
Multichannel, low nonlinearity time-to-digital converters based on 20 and 28 nm FPGAs
H Chen, DDU Li - IEEE Transactions on Industrial Electronics, 2018 - ieeexplore.ieee.org
This paper presents low nonlinearity, compact, and multichannel time-to-digital converters
(TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays …
(TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays …
Efficient implementation of multiple time coding lines-based TDC in an FPGA device
P Kwiatkowski, R Szplet - IEEE Transactions on Instrumentation …, 2020 - ieeexplore.ieee.org
This article presents two principles that make multiple time coding lines (TCLs)-based time-
to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device …
to-digital converter (TDC) implementation in field-programmable gate array (FPGA) device …
A low-resources TDC for multi-channel direct ToF readout based on a 28-nm FPGA
M Parsakordasiabi, I Vornicu, Á Rodríguez-Vázquez… - Sensors, 2021 - mdpi.com
In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-
digital converter (TDC) architecture to achieve high performance with low usage of …
digital converter (TDC) architecture to achieve high performance with low usage of …
Efficient time-to-digital converters in 20 nm FPGAs with wave union methods
The wave union (WU) method is a well-known method in time-to-digital converters (TDCs)
and can improve TDC performances without consuming extra logic resources. However, an …
and can improve TDC performances without consuming extra logic resources. However, an …
Estimating relationship between the time over threshold and energy loss by photons in plastic scintillators used in the J-PET scanner
S Sharma, J Chhokar, C Curceanu, E Czerwiński… - EJNMMI physics, 2020 - Springer
Purpose The time-over-threshold (TOT) technique is being used widely due to
itsimplications in developing the multi-channel readouts, mainly when fast signal processing …
itsimplications in developing the multi-channel readouts, mainly when fast signal processing …
An enhanced fuzzy controller based on improved genetic algorithm for speed control of DC motors
Because of being imprecision and existence of uncertainty in input variables to fuzzy
systems, and also their easy implementation, fuzzy controllers are introduced as one of …
systems, and also their easy implementation, fuzzy controllers are introduced as one of …