A review on energy efficiency and demand response with focus on small and medium data centers

TL Vasques, P Moura, A de Almeida - Energy Efficiency, 2019 - Springer
Data centers are the backbone of a growing number of activities in modern economies.
However, the large increase of digital content, big data, e-commerce, and Internet traffic is …

Proof-of-concept real-time implementation of interleavers for optical satellite links

DR Arrieta, S Almonacil, JM Conan… - Journal of Lightwave …, 2023 - ieeexplore.ieee.org
Ground-satellite optical links are a promising technology for increasing capacity and security
over radio frequency links, while reducing weight and power consumption. However …

NVDIMM-C: A byte-addressable non-volatile memory module for compatibility with standard DDR memory interfaces

C Lee, W Shin, DJ Kim, Y Yu, SJ Kim… - … Symposium on High …, 2020 - ieeexplore.ieee.org
Currently, there are two representative non-volatile dual in-line memory module (NVDIMM)
interfaces: a proprietary Intel DDR-T and the JEDEC NVDIMM-P, which are not supported by …

[PDF][PDF] Design and analysis of a 32-bit pipelined MIPS RISC processor

P Indira, M Kamaraju, VV Dwivedi - International Journal of VLSI …, 2019 - researchgate.net
Pipelining is a technique that exploits parallelism, among the instructions in a sequential
instruction stream to get increased throughput, and it lessens the total time to complete the …

高速图像压缩系统中DDR3 控制器的实现

陈占良, 金龙旭, 陶宏江, 韩双丽 - 2016 - ir.ciomp.ac.cn
摘要数字遥感图像具有数据量大, 实时处理等特点, 为了满足实时图像处理系统对大容量和高
带宽存储系统的需求, 利用spartan6 系列FPGA 内嵌的DDR3 控制器IP 核实现对DDR3 …

Hmem: A Holistic Memory Performance Metric for Cloud Computing

Y Li, N Li, Y Zhang, J Guo, B Huang, M Xing… - International Symposium …, 2023 - Springer
With the proliferation of cloud computing, cloud service providers offer users a variety of
choices in terms of pricing and computing performance. A critical factor impacting computing …

[图书][B] Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping

PA Mayekar - 2019 - search.proquest.com
Abstract System on chip (SoC) designers today are emphasizing on a process which can
ensure robust silicon at the first tape-out. Given the complexity of modern SoC chips, there is …

The DSP and DDR4 VLSI Design for Multi-Sensor in Biomedical System

JS Zhang, CA Chen, SL Chen… - 2023 Asia Pacific Signal …, 2023 - ieeexplore.ieee.org
DDR4 is a high-speed memory structure commonly employed in modern medical devices.
The benefit of DDR4 architecture enables fast data transmission and efficient data …

Data-Flow Modeling of SDRAM with Bank Group in Sequential Access with Intermittent Address Jumps Mode

G Xiao, Y Xiao, K Liu, Z Fu… - 2023 IEEE 16th …, 2023 - ieeexplore.ieee.org
As double data rate synchronous dynamic random-access memory (DDR SDRAM) iterations
continue, the hardware response rate is unable to keep up with the increase in frequency. In …

[HTML][HTML] 工业物联网中的缓冲内存管理设计与实现

吴超, 王成群, 朱升宏, 徐伟强, 贾宇波 - 物联网学报, 2019 - infocomm-journal.com
摘要针对工业物联网高速通信中出现流量堵塞如何高效存储的问题, 引入了内存管理的方法.
在研究同步动态随机存储器(SDRAM) 存储原理的基础上, 设计了一种基于现场可编程逻辑门 …