In the present study, a new structure (0.5–18 GHz) with excellent phase noise characteristics
and a fast switching speed is proposed. Ultra-wideband synthesizers with low phase noises …

A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to
store control input for the oscillator. The PLL is operable in a calibration mode in which the …

A synthesizer comprises a two-point modulation phase locked tow, TPM PLL, circuit
configured to receive a frequency tuning signal and to generate a stepped chirp signal in an …

Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a
phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and …

The next-generation mm/sub-mm/far-IR astronomy will in part be enabled by advanced
digital signal processing (DSP) techniques. The Prime-Cam instrument of the Fred Young …

A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an
oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase …

A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is
presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output …

Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked
loop. An offset signal can be applied to adjust an input signal provided to an integrator of a …

Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust
output phase using a phase adjustment signal. In certain embodiments, the phase …

(57) ABSTRACT A synthesizer comprises a first two-point modulation phase locked loop,
TPM PLL, circuit that receives a first reference clock signal at a first reference frequency and …