Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …

Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …

Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described.
Embodiments are described that use a self-aligned double patterning method for one or …

We present a leakage current replica (LCR) keeper for dynamic domino gates that uses an
analog current mirror to replicate the leakage current of a dynamic gate pull-down stack and …

A 512times13 bit ultra-low-power subthreshold memory is fabricated on a 130-nm process
technology. The fabricated memory is fully functional for read operation with a 190-mV …

ElastIC must deal with extremes a multiple core processor subjected to huge process
variations, transistor degradations at varying rates, and device failures. In this article, we …

While CMOS technology has served semiconductor industry marvelously (by allowing nearly
exponential increase in performance and device integration density), it faces some major …

This paper describes a process compensating dynamic (PCD) circuit technique for
maintaining the performance benefit of dynamic circuits and reducing the variation in delay …

In this paper, a new leakage-tolerant domino circuit is presented which has lower power
consumption and higher noise immunity without significant delay increment for wide fan-in …

As the clock frequency and physical address space of 64-bit microprocessors continue to
grow, one major critical path is the access to the on-die cache memory that includes a tag …