An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an
aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford …

An 8-bit 10-GHz 8× time-interleaved successive-approximation-register (SAR) analog-to-
digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter …

This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for
low-power applications. To tolerate the severe variations in the subthreshold regime, a novel …

Memory-centric designs deploy computation to storage and enable efficient in-memory
computation while avoiding massive amount of data movement. The in-memory-computing …

An asynchronous successive approximation register (SAR) ADC incorporates a passive
resistor based delay cell to reduce power consumption and accommodate the SAR ADC …

Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-
digital converter (ADC) is an attractive design choice for low-power ADC implements. In …

A detector connected to a charge amplifier adds parasitic input capacitance that alters the
amplifier's gain. The detector capacitance therefore must be characterized so as to properly …

Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-
digital converter (ADC) is an attractive design choice for low-power ADC implements. In …

This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold
(STH) architecture. The design aims to address the common timing issue of divider‐based …

A three-step tapered bit period asynchronous successive approximation register (SAR)
analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7 …