Parallel and distributed normalization of security events for instant attack analysis
When looking at media reports nowadays, major security breaches of big companies and
governments seem to be a normal situation. An important step for the investigation or even …
governments seem to be a normal situation. An important step for the investigation or even …
Implementation and evaluation of modular neural networks in a multiple processor system on chip to classify electric disturbance
DC Lopes, RM Magalhaes, JD Melo… - 2009 International …, 2009 - ieeexplore.ieee.org
This paper shows the effectiveness of modular neural networks composed of multilayers
experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The …
experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The …
Self-reconfigurable secure file system for embedded Linux
With the growth of the portable electronic devices market, not only the protection of the data
for the users but also the security of the designs themselves has grown significantly in …
for the users but also the security of the designs themselves has grown significantly in …
[图书][B] Efficient Runtime Management of Reconfigurable Hardware Resources.
T Marconi - 2011 - researchgate.net
Runtime reconfigurable systems built upon devices with partial recon-figuration can provide
reduction in overall hardware area, power efficiency, and economic cost in addition to the …
reduction in overall hardware area, power efficiency, and economic cost in addition to the …
Implementation of a modular neural network in a multiple processor system on FPGA to classify electric disturbance
DC Lopes, RM Magalhães, JD Melo… - 2009 35th Annual …, 2009 - ieeexplore.ieee.org
This paper shows the effectiveness of a modular neural network composed of multilayers
experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The …
experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The …
Implementation of a SigmaBoost-based ensemble of SVM in a multiple processor system on chip
DC Lopes, NHC Lima, JD de Melo… - 2010 VI Southern …, 2010 - ieeexplore.ieee.org
This paper shows the effectiveness of a classifier ensemble composed of weak classifiers
trained with a boosting algorithm implemented in a multiprocessor system on chip. The …
trained with a boosting algorithm implemented in a multiprocessor system on chip. The …
An architecture for dynamically reconfigurable real time audio processing systems
F Bruschi, V Rana, D Sciuto - 2008 IEEE/ACM/IFIP Workshop …, 2008 - ieeexplore.ieee.org
In this paper we present an FPGA-based reconfigurable architecture for real time
elaboration of audio streams. The architecure allows to dynamically define chains of …
elaboration of audio streams. The architecure allows to dynamically define chains of …
[PDF][PDF] Survey of FPGA applications in the period 2000–2015 (Technical Report)
J Romoth, M Porrmann, U Rückert - 2017 - researchgate.net
Since their introduction, FPGAs can be seen in more and more different fields of
applications. The key advantage is the combination of software-like flexibility with the …
applications. The key advantage is the combination of software-like flexibility with the …
Implementation of a Modular Neural Network in a Multiple Processor System on Chip to Classify Electric Disturbance
DC Lopes, RM Magalhães, JD de Melo… - The Fifth International …, 2009 - scitepress.org
This paper shows the effectiveness of a modular neural network composed of multilayers
experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The …
experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The …
A SIMPLE FRAMEWORK FOR DYNAMIC PARTIAL RECONFIGURATION.
M Kvas, S Valach - Annals of DAAAM & Proceedings, 2009 - search.ebscohost.com
The framework described in this paper has been designed to support experiments with
dynamic partial reconfiguration (PR) of FPGA in heterogeneous systems consisting of digital …
dynamic partial reconfiguration (PR) of FPGA in heterogeneous systems consisting of digital …