Layer transfer process and functionally enhanced integrated circuits produced thereby
BK Furman, S Purushothaman… - US Patent …, 2010 - Google Patents
Interconnect challenges for future microprocessors and other high performance chips arise
from the continued push to lower k-effective of interlevel dielectric materials, higher aspect …
from the continued push to lower k-effective of interlevel dielectric materials, higher aspect …
Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
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Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
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transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
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Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Method for fabrication of a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2010-12-03 Assigned to NuPGA Corporation reassignment NuPGA Corporation
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Stacked microelectronic assemblies having vias extending through bond pads
M Kriman, O Avsian, B Haba, G Humpston… - US Patent …, 2013 - Google Patents
A stacked microelectronic assembly is provided which includes first and second stacked
microelectronic elements. Each of the first and second microelectronic elements can include …
microelectronic elements. Each of the first and second microelectronic elements can include …
Semiconductor system and device
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 9,219,005, 2015 - Google Patents
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Semiconductor system and device - Google Patents Semiconductor system and device …
Semiconductor system and device - Google Patents Semiconductor system and device …