Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications
In this paper, the performance boundaries and corresponding tradeoffs of a complex dual-
mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the …
mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the …
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
This paper presents AIDA, an analog integrated circuit design automation environment,
which implements a design flow from a circuit-level specification to physical layout …
which implements a design flow from a circuit-level specification to physical layout …
[图书][B] Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
Over the past few decades, very large scale integration technologies have been widely
improved, allowing the proliferation of consumer electronics and enabling the steady growth …
improved, allowing the proliferation of consumer electronics and enabling the steady growth …
Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits
T Liao, L Zhang - 2017 22nd Asia and South Pacific Design …, 2017 - ieeexplore.ieee.org
In this paper, an efficient parasitic-aware geometric programming and many-objective
evolution algorithm based two-phase hybrid sizing methodology is presented. It considers …
evolution algorithm based two-phase hybrid sizing methodology is presented. It considers …
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation
This paper presents AIDA 2015, the newest version of AIDA, an analog integrated circuit
design automation environment, which implements a design flow from a circuit-level …
design automation environment, which implements a design flow from a circuit-level …
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques
Typically the design of a Radio-Frequency (RF) circuit is difficult, time-consuming and often
based around an iterative process. In this manuscript, an automatic synthesis of three typical …
based around an iterative process. In this manuscript, an automatic synthesis of three typical …
Optimising operational amplifiers by evolutionary algorithms and gm/Id method
E Tlelo-Cuautle… - International Journal of …, 2016 - Taylor & Francis
The evolutionary algorithm called non-dominated sorting genetic algorithm (NSGA-II) is
applied herein in the optimisation of operational transconductance amplifiers. NSGA-II is …
applied herein in the optimisation of operational transconductance amplifiers. NSGA-II is …
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology
In this paper a design strategy based on bottom-up design methodologies is used in order to
systematically design a voltage controlled oscillator. The methodology uses two computer …
systematically design a voltage controlled oscillator. The methodology uses two computer …
A folded voltage-combiners biased amplifier for low voltage and high energy-efficiency applications
The topic of this brief is a single-stage amplifier biased by a doublet of voltage-combiners in
a folded configuration, in order to be supplied by a power source of 1.2 V, maintaining …
a folded configuration, in order to be supplied by a power source of 1.2 V, maintaining …
Current-flow and current-density-aware multi-objective optimization of analog IC placement
In this paper, the concept of hierarchical multi-objective optimization is applied to analog
integrated circuit placement automation, where current-flow and current-density …
integrated circuit placement automation, where current-flow and current-density …