[图书][B] Sub-threshold design for ultra low-power systems
Although energy dissipation has improved with each new technology node, because SoCs
are integrating tens of million devices on-chip, the energy expended per operation has …
are integrating tens of million devices on-chip, the energy expended per operation has …
A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation
BH Calhoun, AP Chandrakasan - IEEE journal of solid-state …, 2007 - ieeexplore.ieee.org
Low-voltage operation for memories is attractive because of lower leakage power and active
energy, but the challenges of SRAM design tend to increase at lower voltage. This paper …
energy, but the challenges of SRAM design tend to increase at lower voltage. This paper …
Scaling trends of digital single-event effects: A survey of SEU and SET parameters and comparison with transistor performance
D Kobayashi - IEEE Transactions on Nuclear Science, 2020 - ieeexplore.ieee.org
The history of integrated circuit (IC) development is another record of human challenges
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …
involving space. Efforts have been made to protect ICs from sudden malfunctions due to …
Multi-bit error tolerant caches using two-dimensional error coding
In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make
embedded memories increasingly vulnerable to reliability and yield problems. As scaling …
embedded memories increasingly vulnerable to reliability and yield problems. As scaling …
Design considerations for ultra-low energy wireless microsensor nodes
This tutorial paper examines architectural and circuit design techniques for a microsensor
node operating at power levels low enough to enable the use of an energy harvesting …
node operating at power levels low enough to enable the use of an energy harvesting …
Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design
A novel mechanism for upset is seen in a commercially available 0.25/spl mu/m 10-T SEE
hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions …
hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions …
Memory mapped ECC: Low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of
providing error correction for SRAM caches. It is important to limit such overheads as …
providing error correction for SRAM caches. It is important to limit such overheads as …
[PDF][PDF] Technology scaling and soft error reliability
LW Massengill, BL Bhuva… - 2012 IEEE …, 2012 - reliablemicrosystems.com
Technology Scaling and Soft Error Reliability Page 1 Technology Scaling and Soft Error
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …
Transient fault models and AVF estimation revisited
Transient faults (also known as soft-errors) resulting from high-energy particle strikes on
silicon are typically modeled as single bit-flips in memory arrays. Most Architectural …
silicon are typically modeled as single bit-flips in memory arrays. Most Architectural …
Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology
BD Olson, OA Amusan, S Dasgupta… - … on Nuclear Science, 2007 - ieeexplore.ieee.org
Three-dimensional TCAD models are used in mixed-mode simulations to analyze the
effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct …
effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct …