A review of three‐dimensional resistive switching cross‐bar array memories from the integration and materials property points of view
Issues in the circuitry, integration, and material properties of the two‐dimensional (2D) and
three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are …
three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are …
Architecture and process integration overview of 3D NAND flash technologies
In the past few decades, NAND flash memory has been one of the most successful
nonvolatile storage technologies, and it is commonly used in electronic devices because of …
nonvolatile storage technologies, and it is commonly used in electronic devices because of …
Three-dimensional NAND flash architecture design based on single-crystalline stacked array
Y Kim, JG Yun, SH Park, W Kim, JY Seo… - … on Electron Devices, 2011 - ieeexplore.ieee.org
Various critical issues related with 3-D stacked nand Flash memory are examined in this
paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better …
paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better …
Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Integration methods to fabricate internal spacers for nanowire devices
S Kim, KJ Kuhn, T Ghani, AS Murthy… - US Patent …, 2016 - Google Patents
A nanowire device having a plurality of internal spacers and a method for forming said
internal spacers are disclosed. In an embodiment, a semiconductor device comprises a …
internal spacers are disclosed. In an embodiment, a semiconductor device comprises a …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system
Brain-inspired neuromorphic systems have attracted much attention as new computing
paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with …
paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …