Multi-core devices for safety-critical systems: A survey

JP Cerrolaza, R Obermaisser, J Abella… - ACM Computing …, 2020 - dl.acm.org
Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …

Drain: Deadlock removal for arbitrary irregular networks

M Parasar, H Farrokhbakht, NE Jerger… - … Symposium on High …, 2020 - ieeexplore.ieee.org
Correctness is a first-order concern in the design of computer systems. For multiprocessors,
a primary correctness concern is the deadlock-free operation of the network and its …

Evolution of Efficient On-Chip Interconnect Architecture for SOC: A Review

N Batra, B Singh - 2022 IEEE Global Conference on Computing …, 2022 - ieeexplore.ieee.org
Constant improvements in transistor technology have made it possible for computer design
to support ever-increasing numbers of processing cores on a single silicon die. With the …

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

VA Delgado-Gallardo, R Sandoval-Arechiga… - IEEE …, 2023 - ieeexplore.ieee.org
The design of Networks-on-Chip (NoCs) components implies a wide range of techniques
and methods to address the microarchitecture of the packet-forwarding components, where …

Highly fault-tolerant NoC routing with application-aware congestion management

D Lee, R Parikh, V Bertacco - … of the 9th International Symposium on …, 2015 - dl.acm.org
Silicon devices are becoming less and less reliable as technology moves to smaller feature
sizes. As a result, digital systems are increasingly likely to experience permanent failures …

An online and real-time fault detection and localization mechanism for network-on-chip architectures

K Chrysanthou, P Englezakis, A Prodromou… - ACM Transactions on …, 2016 - dl.acm.org
Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability
threats. The need to detect and localize the occurrence of faults at runtime is steadily …

An energy-efficient NoC router with adaptive fault-tolerance using channel slicing and on-demand TMR

C Li, M Yang, P Ampadu - IEEE Transactions on Emerging …, 2016 - ieeexplore.ieee.org
The competing goals of energy-efficiency, performance, and fault tolerance have not been
well bridged in current NoC designs. In this paper, we propose an energy-efficient NoC …

Energy‐efficient fault tolerant technique for deflection routers in two‐dimensional mesh Network‐on‐Chips

SZ Sleeba, J Jose, MG Mini - IET Computers & Digital …, 2018 - Wiley Online Library
New generation multi‐processor system‐on‐chips integrate hundreds of processing
elements in a single chip which communicate with each other through on‐chip …

Abacus turn model-based routing for NoC interconnects with switch or link failures

P Bahrebar, D Stroobandt - Microprocessors and Microsystems, 2018 - Elsevier
With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming
more susceptible to faults. Therefore, designing reliable and efficient routing methods is of …

Accurate system-level TSV-to-TSV capacitive coupling fault model for 3D-NoC

PM Yaghini, A Eghbal, SS Yazdi… - Proceedings of the 9th …, 2015 - dl.acm.org
TSV-based 3D-NoC has been introduced as a viable solution for integrating more cores on
a chip, while imposing smaller footprint area and better timing performance as compared to …