Vertically stacked dual channel nanosheet devices
(57) ABSTRACT A semiconductor structure having electrostatic control and a low threshold
voltage is provided. The structure includes an nFET containing vertically stacked and …
voltage is provided. The structure includes an nFET containing vertically stacked and …
Fabrication of vertical fin transistor with multiple threshold voltages
K Balakrishnan, K Cheng, P Hashemi… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A vertical fin field effect transistor including a doped region in a substrate,
wherein the doped region has the same crystal orientation as the substrate, a first portion of …
wherein the doped region has the same crystal orientation as the substrate, a first portion of …
Fabrication of vertical fin transistor with multiple threshold voltages
K Balakrishnan, K Cheng, P Hashemi… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A vertical fin field effect transistor including a doped region in a substrate,
wherein the doped region has the same crystal orientation as the substrate, a first portion of …
wherein the doped region has the same crystal orientation as the substrate, a first portion of …
Vertically stacked dual channel nanosheet devices
SUMMARY A semiconductor structure having electrostatic control and a low threshold
voltage is provided. The structure includes an nlET containing vertically stacked and …
voltage is provided. The structure includes an nlET containing vertically stacked and …
Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
(57) ABSTRACT A method of forming a semiconductor structure includes forming a
semiconductor layer stack including a substrate and a nanosheet channel stack including …
semiconductor layer stack including a substrate and a nanosheet channel stack including …
Method and structure for forming vertical transistors with various gate lengths
K Cheng, S Mochizuki, CH Lee, J Li - US Patent 10,475,923, 2019 - Google Patents
Various methods and structures for fabricating a plurality of vertical fin FETs on the same
semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is …
semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is …
Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors
(57) ABSTRACT A semiconductor device and a method for fabricating the same. The
semiconductor device includes at least an-type vertical FET and ap-type vertical FET. The n …
semiconductor device includes at least an-type vertical FET and ap-type vertical FET. The n …
Self-limiting liners for increasing contact trench volume in n-type and p-type transistors
K Cheng, CH Lee, J Li, P Xu - US Patent 11,183,430, 2021 - Google Patents
Embodiments of the invention include semiconductor devices having a first n-type S/D
region, a second n-type S/D region, and a first layer of protective material over the second n …
region, a second n-type S/D region, and a first layer of protective material over the second n …
Integration of semiconductor structures
K Wostyn - US Patent 10,515,855, 2019 - Google Patents
At least one embodiment relates to a method for integrating Si-Ge, structures with Si-. Geēr
structures in a semicon ductor device. The method includes providing a device that includes …
structures in a semicon ductor device. The method includes providing a device that includes …
Multigate device with stressor layers and method of fabricating thereof
KH Fung - US Patent App. 17/446,420, 2023 - Google Patents
WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese (2+); methyl n-[[2-(
methoxycarbonylcarbamothioylamino) phenyl] carbamothioyl] carbamate; n-[2 …
methoxycarbonylcarbamothioylamino) phenyl] carbamothioyl] carbamate; n-[2 …