An on-chip network has become a powerful platform for solving complex and large-scale
computation problems in the present decade. However, the performance of bus-based …

Abstract System-on-chip designs for high-performance computing systems widely use
network-on-chip (NoC) technology. The critical metrics such as latency, throughput, and total …

Due to high integration density and technology scaling, the manycore networks-on-chip
(NoCs) often experience higher evaluation time by traditional simulations for a set of …

Network-on-Chips (NoCs) have been viewed as a promising alternative to traditional on-
chip communication architecture for the increasing number of IPs in modern chips. To …

Abstract The popularity of Machine Learning (ML) has extended to numerous disciplines,
including the domain of Network-on-chips (NoCs), leading to a consequential impact …

Latency is one of the critical performance metrics for Networks-on-Chips (NoCs). When
designing an NoC, the designers have to explore enormous design parameters and various …

A network-on-chip (NoC) performance is traditionally evaluated using a cycle-accurate
simulator. However, when the NoC size increases, the time required for providing the …

Analog computing-in-memory (ACiM) technology has shown strong potential for neural
network accelerators, addressing von-Neumann performance bottlenecks with in-memory …

For System-on-Chip (SoC) designs, Network-on-Chip (NoC) provides a scalable and
promising interconnect solution that is particularly well-suited for high-performance …

The on-chip network, commonly known as network-on-chip (NoC) on a die as an alternate
prevalent interconnection infrastructure, has been continuously occupying the space of …