AVS3 decoder architecture and VLSI implementation for 8K UHDTV application

HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques

X Zhao, L Chang, D Fan, Z Hu, T Yue… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Super-resolution (SR) techniques have been employed to construct high-definition images
from low-quality images. Various neural networks have demonstrated excellent image …
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Prediction-Reconstruction VLSI architecture with efficient pipelining for VVC Decoder

M Lee, I Kim, P Shin, H Oh, K Joe - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
Versatile Video Coding (VVC) introduced newly proposed tools to improve the compression
rate of ultra-high definition video. However, this increases both the complexity of decoder …
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Optimized Hardware Architecture of Tile to Raster Scan Buffer for Video Decoder and Display Processor

HS Seong, C Jung - 2023 IEEE International Conference on …, 2023 - ieeexplore.ieee.org
As market is driving larger-sized TVs and display devices, video compression codec and
video image processing algorithm are being developed with higher (4K to 8K) video …
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Assistant Cache design to minimize SoC System Bandwidth inefficiency caused by Partial Traffic of Legacy Reused IP

H An, J Moon, J Park, HS Seong… - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
This paper presents a method of minimizing inefficiency of SoC system bandwidth that
generated from reused Legacy IP through an Assistant Cache with flexible line size. As the …
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Efficient Digital Television System Booting Method

DK Lim, HS Seong, C Jung - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
This paper presents Booting procedure and insight of Digital Television System. Compared
to computer, Digital Television System requires low-power mode in WAIT-state and normal …
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