High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2m)

B Rashidi, R Rezaeian Farashahi… - IET Information …, 2017 - Wiley Online Library
In this study high‐performance and high‐speed field‐programmable gate array (FPGA)
implementations of polynomial basis Itoh–Tsujii inversion algorithm (ITA) over GF (2m) …

Low-complexity digit-serial and scalable SPB/GPB multipliers over large binary extension fields using (b, 2)-way Karatsuba decomposition

CY Lee, CS Yang, BK Meher… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two variations
of polynomial basis representation. SPB/GPB have potential for efficient bit-level and digit …

Fixed and dynamic threshold selection criteria in energy detection for cognitive radio communication systems

A Kumar, P Thakur, S Pandit… - 2017 Tenth International …, 2017 - ieeexplore.ieee.org
Spectrum sensing is a key step in cognitive radio communication systems. The probability of
detection and probability of false-alarm are two crucial performance parameters in spectrum …

An area-efficient bit-serial sequential polynomial basis finite field GF (2m) multiplier

SR Pillutla, L Boppana - AEU-International Journal of Electronics and …, 2020 - Elsevier
Many cryptographic and error control coding algorithms rely on finite field arithmetic.
Hardware implementation of these algorithms requires an efficient realization of finite field …

Throughput/area efficient implementation of scalable polynomial basis multiplication

B Rashidi - Journal of Hardware and Systems Security, 2020 - Springer
In this paper, a scalable throughput/area efficient hardware implementation of polynomial
basis multiplication based on a digit-digit structure is presented. To compute multiplication …

Low-Complexity Multiplier for Based on All-One Polynomials

J Xie, PK Meher, J He - IEEE transactions on very large scale …, 2012 - ieeexplore.ieee.org
This paper presents an area-time-efficient systolic structure for multiplication over GF (2 m)
based on irreducible all-one polynomial (AOP). We have used a novel cut-set retiming to …

Area/performance trade-off analysis of an FPGA digit-serial GF (2m) Montgomery multiplier based on LFSR

M Morales-Sandoval, C Feregrino-Uribe… - Computers & Electrical …, 2013 - Elsevier
Montgomery Multiplication is a common and important algorithm for improving the efficiency
of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A …

Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction

A Ibrahim, F Gebali - Journal of Signal Processing Systems, 2016 - Springer
We present low area and low power semi-systolic array architectures for polynomial basis
multiplication over GF (2 m) using Progressive Multiplier Reduction Technique (PMR) …

New digit-serial three-operand multiplier over binary extension fields for high-performance applications

CY Lee, CC Fan, SM Yuan - 2017 2nd IEEE International …, 2017 - ieeexplore.ieee.org
Digit-serial polynomial basis multipliers over GF (2 m) are broadly applied in elliptic curve
cryptography, because squaring and polynomial reduction in GF (2 m) are simple …

A scalable digit-parallel polynomial multiplier architecture for NIST-standardized binary elliptic curves

H Kumar, M Rashid, A Alhomoud, SZ Khan, I Bahkali… - Applied Sciences, 2022 - mdpi.com
This work presents a scalable digit-parallel finite field polynomial multiplier architecture with
a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit …