[PDF][PDF] 采用自适应连续时间线性均衡器和判决反馈均衡器算法的一种16 Gbit/s 并转串/串转并接口
文溢， 陈建军， 黄俊， 姚啸虎， 刘衡竹 - 电子与信息学报, 2023 - jeit.ac.cn
该文在体硅CMOS 工艺下设计了一种16 Gbit/s 并转串/串转并接口(SerDes) 芯片, 该SerDes
由4 个通道(lanes) 和2 个锁相环(PLLs) 组成. 在接收器模拟前端(AFE) 采用负阻抗结构连续时间 …
由4 个通道(lanes) 和2 个锁相环(PLLs) 组成. 在接收器模拟前端(AFE) 采用负阻抗结构连续时间 …
Design of Crosstalk Prevention Coding scheme based on Quintuplicated Manchester error correction method for Reliable on chip Interconnects
P Narayanasamy, S Muthurathinam… - … in Electrical and …, 2018 - search.proquest.com
A low power Manchester based error-control code for on-chip interconnection-link has been
proposed in this paper. It has a capacity to rectify nonuple errors of random and burst using …
proposed in this paper. It has a capacity to rectify nonuple errors of random and burst using …
A 16 Gbit/s Serializer/Deserializer with Adaptive Continuous Time Linear Equalizer and Decision Feedback Equalizer Equalization Algorithm
Y WEN, J CHEN, J HUANG, X YAO, H LIU - 电子与信息学报, 2023 - jeit.ac.cn
Abstract A 16 Gbit/s Serializer/Deserializer interface (SerDes) chip which is composed of 4
lanes and 2 Phase-Locked Loop (PLLs), is designed in bulk CMOS technology. A negative …
lanes and 2 Phase-Locked Loop (PLLs), is designed in bulk CMOS technology. A negative …
Performance comparison between SerDes and time-based serial links
M Rashdan, F El-Sayed… - 2020 7th international …, 2020 - ieeexplore.ieee.org
This paper presents a Performance comparison between the SerDes architecture and the
time-based architectures. The challenges and the drawbacks in designing both architectures …
time-based architectures. The challenges and the drawbacks in designing both architectures …
[PDF][PDF] Design and Analysis of Low Power Universal Line Encoder & Decoder
Communication plays an important role in day to day life. The information or data is
transmitted through various techniques and line coding is one of the finest techniques for …
transmitted through various techniques and line coding is one of the finest techniques for …
1.5 µW wake‐up‐receiver for biotelemetry applications
SE Whitehall, CE Saavedra - Microwave and Optical …, 2017 - Wiley Online Library
This article presents a microwave wake‐up receiver for biotelemetry applications. The circuit
is designed using 130 nm CMOS technology and it consists of a passive amplification front …
is designed using 130 nm CMOS technology and it consists of a passive amplification front …
A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme
This paper presents a 24 Gbps SerDes transceiver circuit for on-chip high speed serial links
for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level …
for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level …
[HTML][HTML] Design of a new serializer and deserializer architecture for on-chip SerDes transceivers
The increasing trends in SoCs and SiPs technologies demand integration of large numbers
of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising …
of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising …
Low-power, low-latency transceiver design using d-TGMS flip-flop for on-chip interconnects
The routers in Network on Chips (NoCs) are used to transmit the data among the Processing
Elements (PEs) in the field, and it can be done through transmission links between the …
Elements (PEs) in the field, and it can be done through transmission links between the …
Low power communication RFIC design for applications in biotelemetry
S Whitehall - 2018 - search.proquest.com
Low Power Communication RFIC Design For Applications In Biotelemetry Page 1 Low Power
Communication RFIC Design For Applications In Biotelemetry by Sean Whitehall A thesis …
Communication RFIC Design For Applications In Biotelemetry by Sean Whitehall A thesis …