[图书][B] Low-power electronics design
C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …
affecting the design of high-performance chips and portable devices. The study of power …
A post-compiler approach to scratchpad mapping of code
F Angiolini, F Menichelli, A Ferrero, L Benini… - Proceedings of the …, 2004 - dl.acm.org
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are
more energy-efficient than caches and enable tighter application control on the memory …
more energy-efficient than caches and enable tighter application control on the memory …
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-
compromise solution when taking into account performance, energy consumption and die …
compromise solution when taking into account performance, energy consumption and die …
Load/store unit for a processor, and applications thereof
MB Yu, EK Nangia, M Ni - US Patent 9,946,547, 2018 - Google Patents
A load/store unit for a processor, and applications thereof. In an embodiment, the load/store
unit includes a load/store queue configured to store information and data associated with a …
unit includes a load/store queue configured to store information and data associated with a …
System-level optimization of accelerator local memory for heterogeneous systems-on-chip
In modern system-on-chip architectures, specialized accelerators are increasingly used to
improve performance and energy efficiency. The growing complexity of these systems …
improve performance and energy efficiency. The growing complexity of these systems …
An efficient profile-based algorithm for scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-
compromise solution when taking into account performance, energy consumption, and die …
compromise solution when taking into account performance, energy consumption, and die …
System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
XY Jiang - US Patent 7,721,071, 2010 - Google Patents
A processor core and a method for distributive scoreboard scheduling in an out-of-order
processor pipeline are described herein. In an embodiment, control logic appends operand …
processor pipeline are described herein. In an embodiment, control logic appends operand …
Data cache virtual hint way prediction, and applications thereof
MB Yu, EK Nangia, M Ni, V Rajagopalan - US Patent 7,594,079, 2009 - Google Patents
A virtual hint based data cache way prediction scheme, and applications thereof. In an
embodiment, a processor retrieves data from a data cache based on a virtual hint value or …
embodiment, a processor retrieves data from a data cache based on a virtual hint value or …
System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
K Svendsen, M Ukanwa - US Patent 7,647,475, 2010 - Google Patents
5,091,851 A 2f1992 Shelton et al. 5,109.520 A 4, 1992 Knierim 5,325,511 A 6, 1994 Collins
et al. 5,493,523 A 2f1996 Huffman 5,493,667 A 2f1996 Hucket al. 5,510,934 A 4, 1996 …
et al. 5,493,523 A 2f1996 Huffman 5,493,667 A 2f1996 Hucket al. 5,510,934 A 4, 1996 …