In aerospace applications, the continuous scaling of CMOS technology makes SRAM cells
more and more susceptible to soft errors. To overcome this issue, a radiation-hardened …

The static random access memory (SRAM) cells are essential for aerospace applications in
near sub-threshold voltage, and it has challenges for the implementation of SRAM cells for …

We measure neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs)
on Flip-Flops (FFs) in a 65-nm bulk CMOS process in order to evaluate dependence of …

Trigger transistors of the DICE CMOS memory cell can be divided into two groups and
spaced topologically; and if the effect of single nuclear particle affects transistors of only one …

Abstract A CMOS DICE (Dual Interlocked Storage Cell) cell consists of two transistor groups
whose layout on the crystal increases the cell's stability against the impact of single nuclear …

The first experimental test of new DICE memory cells with the transistors spaced into two
groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static …

Single-port (SP) and two-port (TP) SRAM exposure to low-energy protons, alpha particles,
and heavy-ions with varying supply voltages show particle linear energy transfer (LET) …

Первая экспериментальная проверка новых ячеек памяти DICE с разделенными на две
группы транзисторами (Spaced Transistor Groups DICE–STG DICE) в составе 65-нм …

In this work, the efforts of an industry wide consortium to characterize the logic soft error rate
of a multitude of combinational and sequential logic circuits across multiple technologies is …

TCAD моделирование воздействий одиночных ядерных частиц на ячейки памяти STG
DICE с транзисторами, разнесенными на две группы (Spaced Transistor Groups DICE) …