Extratime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level
F Oboril, MB Tahoori - IEEE/IFIP International Conference on …, 2012 - ieeexplore.ieee.org
With shrinking feature sizes, transistor aging due to NBTI and HCI becomes a major
reliability challenge for microprocessors. These processes lead to increased gate delays …
reliability challenge for microprocessors. These processes lead to increased gate delays …
Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability
Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling
and increasing temperatures due to growing power density are threatening lifetime …
and increasing temperatures due to growing power density are threatening lifetime …
Aging-aware voltage scaling
As feature sizes of transistors began to approach atomic levels, aging effects have become
one of major concerns when it comes to reliability. Recently, aging effects have become a …
one of major concerns when it comes to reliability. Recently, aging effects have become a …
Long-term reliability of nanometer VLSI systems
Reliability has become a more serious design challenge for current nanometer very large-
scale integrated (VLSI) circuits especially as the technology has advanced into 7nm. It was …
scale integrated (VLSI) circuits especially as the technology has advanced into 7nm. It was …
Fine-grained aging-induced delay prediction based on the monitoring of run-time stress
Run-time solutions based on online monitoring and adaptation are required for resilience in
nanoscale integrated circuits, as design-time solutions and guard bands are no longer …
nanoscale integrated circuits, as design-time solutions and guard bands are no longer …
Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods
The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …
Applicability of power-gating strategies for aging mitigation of CMOS logic paths
N Khoshavi, RA Ashraf… - 2014 IEEE 57th …, 2014 - ieeexplore.ieee.org
Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of
propagation delay and energy efficiency in nanoscale designs. Recently, Power-gating has …
propagation delay and energy efficiency in nanoscale designs. Recently, Power-gating has …
Towards graceful aging degradation in NoCs through an adaptive routing algorithm
Continuous technology scaling has made aging mechanisms such as Negative Bias
Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip …
Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip …
VarEMU: An emulation testbed for variability-aware software
Modern integrated circuits, fabricated in nanometer technologies, suffer from significant
power/performance variation across-chip, chip-to-chip and over time due to aging and …
power/performance variation across-chip, chip-to-chip and over time due to aging and …
Confronting the variability issues affecting the performance of next-generation SRAM design to optimize and predict the speed and yield
Effectively confronting device and circuit parameter variations to maintain or improve the
design of high performance and energy efficient systems while satisfying historical …
design of high performance and energy efficient systems while satisfying historical …