Implementation of Givens QR-decomposition in FPGA
A Sergyienko, O Maslennikov - International Conference on Parallel …, 2001 - Springer
A new parallel processor structure for Givens QR-decomposition intended for the FPGA
implementation is presented. The structure is derived using method of mapping regular …
implementation is presented. The structure is derived using method of mapping regular …
Fault tolerant qr-decomposition algorithm and its parallel implementation
O Maslennikow, J Kaniewski… - Euro-Par'98 Parallel …, 1998 - Springer
A fault tolerant algorithm based on Givens rotations and a modified weighted checksum
method is proposed for the QR-decomposition of matrices. The algorithm enables us to …
method is proposed for the QR-decomposition of matrices. The algorithm enables us to …
Implementation of Cholesky LLT-decomposition algorithm in FPGA-based rational fraction parallel processor
O Maslennikow, P Ratuszniak… - 2007 14th International …, 2007 - ieeexplore.ieee.org
In this paper, the fixed size processor array architecture, which is destined for realization of
LL T-decomposition of symmetrical positively definite matrices based on Cholesky algorithm …
LL T-decomposition of symmetrical positively definite matrices based on Cholesky algorithm …
Systematic generation of executing programs for processor elements in parallel asic or fpga-based systems and their transformation into vhdl-descriptions of …
O Maslennikov - International Conference on Parallel Processing and …, 2001 - Springer
In this paper, a method for the systematic generation of executing programs for processor
element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this …
element of parallel ASIC or FPGA-based systems like processor arrays is proposed. In this …
[HTML][HTML] A Method for Mapping DSP Algorithms into Pentium MMX™ Architecture
A Sergyienko, J Kaniewski, A Arefjev, D Kortshev - Proc, 1999 - kanyevsky.kpi.ua
AbstractIn the representation a new method for mapping DSP algorithms into MMX
architecture is considered. The method is based on the matrix-graph method for mapping …
architecture is considered. The method is based on the matrix-graph method for mapping …
[PDF][PDF] VHDL-models of parallel fir digital filters
J Kaniewski, R Berezowski, D Gretkowski… - Workshop …, 1999 - academia.edu
In this paper, the problem of the designing of the processor array (PA) architectures for the
DSP problems solution is discussed on the example of the digital FIR-filtering algorithm. At …
DSP problems solution is discussed on the example of the digital FIR-filtering algorithm. At …
[PDF][PDF] Technical University of Koszalin
N Maslennikowa - dlibra.tu.koszalin.pl
1.2. Analysis of known fault tolerance methods and selecting of most suitable from them for
the designing of fault-tolerant VLSI parallel systems 1.3. Requirements to methods of the …
the designing of fault-tolerant VLSI parallel systems 1.3. Requirements to methods of the …
A technique for mapping sparse matrix computations into regular processor arrays
R Wyrzykowski, J Kanevski - Euro-Par'97 Parallel Processing: Third …, 1997 - Springer
A technique for mapping irregular sparse matrix computations into regular parallel networks
is proposed. It is based on regularization of the original irregular graph of an algorithm. For …
is proposed. It is based on regularization of the original irregular graph of an algorithm. For …
[PDF][PDF] Deriving Dependence Graphs of Regular Algorithms and their Transformations–the Main Stage in ASIC and FPGA-based Architectures Design
O Maslennikow - Proc. Int. Conf. ICSES'2000, 2000 - Citeseer
The simple and feasible for CAD implementation method of deriving dependence graphs of
regular algorithms and several examples of pupposive graph transformations are …
regular algorithms and several examples of pupposive graph transformations are …
Implementation of linear algebra algorithms in FPGA-based rational fraction arithmetic units
O Maslennikow, P Ratuszniak… - 2007 9th International …, 2007 - ieeexplore.ieee.org
In this paper, two fixed size processor array architectures, which are destined for realization
of several linear algebra algorithms, are proposed. In order to implementation of these …
of several linear algebra algorithms, are proposed. In order to implementation of these …