PUFKY: A fully functional PUF-based cryptographic key generator
We present PUFKY: a practical and modular design for a cryptographic key generator based
on a Physically Unclonable Function (PUF). A fully functional reference implementation is …
on a Physically Unclonable Function (PUF). A fully functional reference implementation is …
[图书][B] Algebraic codes for data transmission
RE Blahut - 2003 - books.google.com
The need to transmit and store massive amounts of data reliably and without error is a vital
part of modern communications systems. Error-correcting codes play a fundamental role in …
part of modern communications systems. Error-correcting codes play a fundamental role in …
The Development and Progress of the UWB Physical Layer
Ultra-wideband (UWB) technology has been applied in many fields, such as radar and
indoor positioning, because of its advantages of having a high transmission rate, anti …
indoor positioning, because of its advantages of having a high transmission rate, anti …
Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories
W Liu, J Rho, W Sung - 2006 IEEE Workshop on Signal …, 2006 - ieeexplore.ieee.org
As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories,
there is growing call for fast and compact error correction code (ECC) circuit with minimum …
there is growing call for fast and compact error correction code (ECC) circuit with minimum …
VLSI implementation of BCH error correction for multilevel cell NAND flash memory
H Choi, W Liu, W Sung - … on Very Large Scale Integration (VLSI …, 2009 - ieeexplore.ieee.org
Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-
based storage systems. In this paper, low-power and high-throughput error-correction …
based storage systems. In this paper, low-power and high-throughput error-correction …
Error correction for multi-level NAND flash memory using Reed-Solomon codes
Prior research efforts have been focusing on using BCH codes for error correction in multi-
level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel …
level cell (MLC) NAND flash memory. However, BCH codes often require highly parallel …
The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories
D Strukov - 2006 Fortieth Asilomar Conference on Signals …, 2006 - ieeexplore.ieee.org
We have investigated the area and latency tradeoffs with respect to error correcting
capability of fast bit-parallel binary BCH ECC decoders. In particular, we show that for a …
capability of fast bit-parallel binary BCH ECC decoders. In particular, we show that for a …
[图书][B] VLSI architectures for modern error-correcting codes
X Zhang - 2016 - api.taylorfrancis.com
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital
communication and storage system, such as wireless communications, optical …
communication and storage system, such as wireless communications, optical …
A new decoding method for Reed–Solomon codes based on FFT and modular approach
N Tang, YS Han - IEEE Transactions on Communications, 2022 - ieeexplore.ieee.org
Decoding algorithms for Reed–Solomon (RS) codes are of great interest for both practical
and theoretical reasons. In this paper, an efficient algorithm, called the modular approach …
and theoretical reasons. In this paper, an efficient algorithm, called the modular approach …
Reed-solomon decoder systems for high speed communication and data storage applications
H Lee - US Patent App. 11/222,435, 2006 - Google Patents
(57) ABSTRACT A high-speed, low-complexity Reed-Solomon (RS) decoder architecture
using a novel pipelined recursive Modified Euclidean (PrME) algorithm block for very high …
using a novel pipelined recursive Modified Euclidean (PrME) algorithm block for very high …