An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

V Bakhtiary, A Amirany, MH Moaiyeri, K Jafari - Microelectronics Reliability, 2023 - Elsevier
Ternary logic has been investigated for several years as it can provide substantial
advantages in reducing the complexity of operations and the number of interconnects. On …

Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications

S Pal, S Bose, WH Ki, A Islam - IEEE Transactions on Electron …, 2019 - ieeexplore.ieee.org
Smaller, lighter, and cost-effective satellite design is a major field of research today. Since
such satellites are equipped with limited resources, there is a huge demand for low-power …

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

B Rawat, P Mittal - Proceedings of the Royal Society A, 2022 - royalsocietypublishing.org
In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access
memory bit cell is presented. The cell is designed based on a detailed review of various pre …

Design of high-reliability memory cell to mitigate single event multiple node upsets

H Li, L Xiao, C Qi, J Li - … Transactions on Circuits and Systems I …, 2021 - ieeexplore.ieee.org
As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event
Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge …

Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET

A Ray, A Naugarhiya, GP Mishra - Microelectronics Reliability, 2022 - Elsevier
The total ionizing dose (TID) response of SOI-FinFET with linear gate workfunction
modulation is presented and evaluated. The gate metal workfunction is linearly modulated …

Nwise and Pwise: 10T radiation hardened SRAM cells for space applications with high reliability requirements

A Seyedi, S Aunet, PG Kjeldsberg - IEEE Access, 2022 - ieeexplore.ieee.org
SRAM cells are widely used to design memory blocks of, eg, caches, register files, and
translation lookaside buffers. Depending on the SRAM application, the design requirements …

Investigation of radiation hardened TFET SRAM cell for mitigation of single event upset

M Pown, B Lakshmi - IEEE Journal of the Electron Devices …, 2020 - ieeexplore.ieee.org
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel
field effect transistor (DG TFET). The mitigation technique for the data recovery after the …

A survey on two-dimensional Error Correction Codes applied to fault-tolerant systems

D Freitas, C Marcon, J Silveira, L Naviner… - Microelectronics …, 2022 - Elsevier
The number of memory faults operating in radiation environments increases with the
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …

Low‐power and high‐speed 13T SRAM cell using FinFETs

S Saxena, R Mehra - IET Circuits, Devices & Systems, 2017 - Wiley Online Library
Fin field‐effect transistors (FinFETs) are replacing the traditional planar metal–oxide–
semiconductor FETs (MOSFETs) because of superior capability in controlling short channel …

SRAM radiation hardening through self-refresh operation and error correction

MSM Siddiqui, S Ruchi, L Van Le, T Yoo… - … on Device and …, 2020 - ieeexplore.ieee.org
In Space applications, the scaling of transistors has made integrated circuits (ICs) more
susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a …