A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to
store control input for the oscillator. The PLL is operable in a calibration mode in which the …

Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a
phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and …

A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an
oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase …

A novel and useful fully integrated switched-mode wideband 60 GHz power amplifier
architecture. Using an appropriate second-harmonic termination of its output matching …

Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked
loop. An offset signal can be applied to adjust an input signal provided to an integrator of a …

Aspects of this disclosure relate to a digital phase-locked loop (DPLL) arranged to adjust
output phase using a phase adjustment signal. In certain embodiments, the phase …

A digital synthesizer is described that comprises: a ramp generator configured to generate a
signal of frequency control words (FCW), that describes a desired frequency modulated …

An exponentially-scaling switched impedance circuit includes: two or more impedance
scaling circuits, wherein each impedance scaling circuit comprises: an input port; an output …

An oscillator includes: a first inductor; and a programmable capacitor bank coupled between
a first terminal of the first inductor and a second terminal of the first inductor, where the …

(57) ABSTRACT A digitally controlled oscillator (DCO) may include a transformer, which may
contain a secondary winding comprising a first port, a second port, and an array of capacitor …