Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch
VM Srivastava, KS Yadav, G Singh - Microelectronics Journal, 2011 - Elsevier
In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-
Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication …
Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication …
[图书][B] Fundamentals of nanoscaled field effect transistors
A Chaudhry - 2013 - Springer
This book is an outcome of my research publications during my teaching and research
career. The book is about basic understanding of the MOSFET devices and their physics at …
career. The book is about basic understanding of the MOSFET devices and their physics at …
Analytical surface potential-based compact model for independent dual gate a-IGZO TFT
A surface potential-based compact model for independent dual gate (IDG) amorphous In-Ga-
Zn-O thin-film transistors (IDG a-IGZO TFTs) is proposed here. The transport theories of …
Zn-O thin-film transistors (IDG a-IGZO TFTs) is proposed here. The transport theories of …
A new surface potential based compact model for independent dual gate a-IGZO TFT: Experimental verification and circuit demonstration
For the first time, we proposed a continuous analytical surface potential-based compact
model of the independent Dual Gate amorphous In-Ga-Zn-O thin film transistors (IDG a-IGZO …
model of the independent Dual Gate amorphous In-Ga-Zn-O thin film transistors (IDG a-IGZO …
Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory
L Xu, K Chen, Z Li, Y Zhao, L Wang… - IEEE Journal of the …, 2024 - ieeexplore.ieee.org
Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are
promising for long-retention, high-density and low-power 3D DRAM solutions due to its low …
promising for long-retention, high-density and low-power 3D DRAM solutions due to its low …
2D Surface potential and mobility modelling of doped/undoped symmetric double gate MOSFET
R Bose, JN Roy - IET Circuits, Devices & Systems, 2019 - Wiley Online Library
The 2D surface potential and mobility models are proposed for symmetric doped/undoped
channel double gate FET (DGFET) device. This is then used in drain current equation …
channel double gate FET (DGFET) device. This is then used in drain current equation …
A current model for FOI FinFETs with back-gate bias modulation
The current model of FOI (Fin-On-Insulator) FinFETs was developed, in which the back-
channel current was modeled as a parasitic transistor. Both the experimental and TCAD …
channel current was modeled as a parasitic transistor. Both the experimental and TCAD …
A 2‐D surface‐potential‐based threshold voltage model for short channel asymmetric heavily doped DG MOSFETs
In recent times, transistors with heavily doped body have generated much interest because
of junctionless channel. In addition, proper threshold voltage regulation requires adjustment …
of junctionless channel. In addition, proper threshold voltage regulation requires adjustment …
Short-channel drain current model for asymmetric heavily/lightly doped DG MOSFETs
The paper presents a drain current model for double gate metal oxide semiconductor field
effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for …
effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for …
A current model for FOI FinFETs with back-gate bias modulation
FY Zhang, FY Liu, BH Li, C Yang… - … Integration on Silicon …, 2020 - ieeexplore.ieee.org
The current model of FOI (Fin-On-Insulator) FinFETs was developed, in which the back-
channel current was modeled as a parasitic transistor. Both the experimental and TCAD …
channel current was modeled as a parasitic transistor. Both the experimental and TCAD …