Emerging cache-coherent non-uniform memory access (cc-NUMA) architectures provide
cache coherence across hundreds of cores. These architectures change how applications …

Correct transactional memory systems (TMs) must address the possibility that a speculative
transaction may read mutually inconsistent values from memory and then perform an …

Embedded systems design requires the development of complex HW modules to cope with
the most stringent timing constraints of the specifications. This implies the need to update …

Software Transactional Memory (STM) systems are increasingly emerging as a promising
alternative to traditional locking algorithms for implementing generic concurrent applications …

Different formal models of transactional memory are required at different levels of the system
stack. This paper focuses on the run-time level, where the semantics of individual operations …

We present the PaRV tool for runtime detection of and recovery from data races in multi-
threaded C and C++ programs. PaRV uses transactional memory technology for …

As other multithreaded programs, transactional memory (TM) programs are prone to race
conditions. Previous work focuses on extending existing definitions of data race for lock …

Transactional Memory (TM) simplifies concurrent programming by providing atomic,
compositional blocks within which programmers can reason sequentially. Many transactions …

Software Transactional Memory (STM) has recently emerged as a promising
synchronization abstraction for multicore architectures. State-of-the-art STM algorithms …

Manual parallelization is time consuming and error-prone. Automatic parallelization on the
other hand is often unable to extract substantial parallelism. Using speculation, however …