This article presents a process-and temperature-invariant high-resolution and highly linear
low-power phase interpolator (PI) as an enabler for discrete-time spatial signal processors …

This paper provides an in-depth analysis of the third-order bang-bang clock and data
recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the …

In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of a
phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology is …

Recently, there has been a strong drive to replace established analog circuits for multi-
gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase …

This brief describes a passive analog phase interpolator, utilizing a switched RC-network.
The proposed circuit eliminates the current sources in a phase interpolator based on …

In this article, a maximum-eye-tracking clock and data recovery (MET-CDR) circuits for
minimum bit error rate (BER) are presented. The proposed CDR does not require a BER …

This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and
digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond …

This paper presents a digital loop-based CDR endorsed in a SerDes system which can
operate up to 16 Gbps. The proposed CDR employs a dynamic loop-gain control to achieve …

A 100 Gb/s quad-lane SerDes receiver with a phase-interpolator (PI)-based quarter-rate all-
digital clock and data recovery (CDR) is presented. The proposed CDR utilizes a multi …

This brief presents an odd phase Bang-Bang phase detector-based CDR architecture that
has a unique property that the clock phases sampling the data automatically become …