Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods

WE Wang, MS Rodder, RC Bowen - US Patent 9,064,699, 2015 - Google Patents
Methods of forming semiconductor patterns including reduced dislocation defects and
devices formed using Such methods are provided. The methods may include forming an …

Semiconductor fin devices and method of fabricating the semiconductor fin devices

M Cantoro, K TaeYong, S Kim, JH Lee - US Patent 9,318,491, 2016 - Google Patents
(57) ABSTRACT A semiconductor device includes a Substrate, an insulating layer disposed
on the Substrate and having a trench exposing a Surface portion of the Substrate, and a …

Flexible single-crystalline semiconductor device and fabrication methods thereof

JH Ryou - US Patent 9,831,273, 2017 - Google Patents
Abstract Systems and methods herein relate to the fabrication of a single-crystal flexible
semiconductor template that may be attached to a semiconductor device. The template …

Forming a fin using double trench epitaxy

VS Basker, P Hashemi, S Mochizuki… - US Patent …, 2017 - Google Patents
The present invention relates generally to semiconductor devices and more particularly, to a
structure and method of forming a fin using double trench epitaxy. The fin may be composed …

III-V field effect transistor on a dielectric layer

CW Cheng, EW Kiewra, A Majumdar… - US Patent …, 2017 - Google Patents
An electrical device comprising a base semiconductor layer of a silicon including material; a
dielectric layer present on the base semiconductor layer; a first III-V semiconductor material …

Formation of devices by epitaxial layer overgrowth

JM Hydrick, J Li, Z Cheng, J Fiorenza, J Bai… - US Patent …, 2018 - Google Patents
Methods and structures are provided for formation of devices, eg, solar cells, on substrates
including, eg, lat tice-mismatched materials, by the use of aspect ratio trap ping and epitaxial …

Silicon-compatible compound junctionless field effect transistor

B Park, S Cho, IM Kang - US Patent 8,878,251, 2014 - Google Patents
The present invention provides a silicon-compatible compound junctionless field effect
transistor enabled to be compatible to a bulk silicon substrate for substituting an expensive …

Planar III-V field effect transistor (FET) on dielectric layer

CW Cheng, EW Kiewra, A Majumdar, U Rana… - US Patent …, 2016 - Google Patents
A method of forming a semiconductor substrate including a type III-V semiconductor material
directly on a dielectric material that includes forming a trench in a dielectric layer, and …

Complementary metal oxide semiconductor device, optical apparatus including the same, and method of manufacturing the same

SM Lee, YJ Cho - US Patent 9,355,917, 2016 - Google Patents
(57) ABSTRACT A complementary metal oxide semiconductor (CMOS) device includes an n-
type first transistor on a silicon Substrate, the n-type first transistor including a Group III-V …

Method for fabricating a semiconductor structure

D Caimi, L Czornomaz, J Fompeyrine… - US Patent …, 2017 - Google Patents
Method for fabricating a semiconductor structure. The method includes: providing a
crystalline silicon Substrate; defining an opening in a dielectric layer on the crystalline …