Wide tunning range 60 GHz VCO and 40 GHz DCO using single variable inductor

TY Lu, CY Yu, WZ Chen, CY Wu - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning
range DCO incorporating variable inductor (VID) techniques. The variable inductor …

A 31- W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

P Chen, F Zhang, Z Zong, S Hu… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time
converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor …

A CMOS WCDMA/WLAN digital polar transmitter with AM replica feedback linearization

S Zheng, HC Luong - IEEE journal of solid-state circuits, 2013 - ieeexplore.ieee.org
This paper presents a 65 nm CMOS digital polar transmitter with on-chip power amplifier
(PA) for WCDMA and WLAN application. The proposed architecture is composed of a digital …

Pulling mitigation in wireless transmitters

A Mirzaei, H Darabi - IEEE Journal of Solid-State Circuits, 2014 - ieeexplore.ieee.org
A new architecture to mitigate the unwanted pulling effect of a transmitter VCO pulled by its
own transmitted signal or by other on-chip locked oscillators is presented. The proposed …

A digitally controlled injection-locked oscillator with fine frequency resolution

I Bashir, RB Staszewski… - IEEE journal of solid-state …, 2016 - ieeexplore.ieee.org
We propose a digitally controlled injection-locked RF oscillator with an auxiliary loop as an
alternative to the conventional capacitive fine-tuning of an LC-tank. The oscillator is injection …

A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques

Y Liu, H Gao, H Xu, P Lu, N Yan - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This paper presents a power-efficient constant-slope digital-to-time converter (DTC) with
embedded nonlinearity cancellation. By utilizing the capacitor based digital-to-analog …

Study of injection pulling of oscillators in phase-locked loops

T Yoshimura - IEEE Transactions on Very Large Scale …, 2020 - ieeexplore.ieee.org
The injection pulling of oscillators in phase-locked loop (PLL) circuits is analyzed by the
linear approximation of nonlinear differential equations in terms of the oscillator phase …

Toward solving multichannel RF-SoC integration issues through digital fractional division

SARA Mehr, M Tohidian… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip
area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the …

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

K Xu, FW Kuo, HNR Chen, LC Cho… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
In this paper, we propose a sub-gigahertz transmitter (TX) with a physically merged digitally
controlled oscillator (DCO) and digital power amplifier (DPA). The matching transformer of …

Design of a direct conversion transmitter to resist combined effects of power amplifier distortion and local oscillator pulling

CH Hsiao, CT Chen, TS Horng… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
This work elucidates how the combined effects of power-amplifier distortion and local-
oscillator (LO) pulling adversely impact a wireless direct-conversion transmitter (DCT) that …