A low-power accuracy-configurable floating point multiplier
Floating point multiplication is one of the most frequently used arithmetic operations in a
wide variety of applications, but the high power consumption of the IEEE-754 standard …
wide variety of applications, but the high power consumption of the IEEE-754 standard …
Variable precision floating-point multiplier
M Langhammer - US Patent 10,042,607, 2018 - Google Patents
Integrated circuits with specialized processing blocks are provided. The specialized
processing blocks may include floating-point multiplier circuits that can be configured to …
processing blocks may include floating-point multiplier circuits that can be configured to …
Variable precision floating-point multiplier
M Langhammer - US Patent 10,379,815, 2019 - Google Patents
Integrated circuits with specialized processing blocks are provided. The specialized
processing blocks may include floating-point multiplier circuits that can be configured to …
processing blocks may include floating-point multiplier circuits that can be configured to …
Variable precision floating-point multiplier
M Langhammer - US Patent 10,572,222, 2020 - Google Patents
Integrated circuits with specialized processing blocks are provided. The specialized
processing blocks may include floating-point multiplier circuits that can be configured to …
processing blocks may include floating-point multiplier circuits that can be configured to …
Area‐and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA
In this study, an area and power‐efficient iterative floating‐point (FP) multiplier architecture
is designed and implemented on FPGA devices with pipelined architecture. The proposed …
is designed and implemented on FPGA devices with pipelined architecture. The proposed …
Unified architecture for double/two-parallel single precision floating point adder
MK Jaiswal, RCC Cheung… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Floating point (FP) addition is a core operation for a wide range of applications. This brief
presents an area-efficient, dynamically configurable, multiprecision architecture for FP …
presents an area-efficient, dynamically configurable, multiprecision architecture for FP …
Area-efficient architecture for dual-mode double precision floating point division
MK Jaiswal, HKH So - … Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
Floating point division is a core arithmetic widely used in scientific and engineering
applications. This paper proposed an architecture for double precision floating point …
applications. This paper proposed an architecture for double precision floating point …
Multi-mode SpMV accelerator for transprecision PageRank with real-world graphs
With the development of Internet networks, the PageRank algorithm, which was initially
developed to recommend important pages in Google's web search systems, is widely used …
developed to recommend important pages in Google's web search systems, is widely used …
Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
Floating point multiplication is one of the crucial operations in many application domains
such as image processing, signal processing etc. But every application requires different …
such as image processing, signal processing etc. But every application requires different …
Configurable architectures for multi-mode floating point adders
This paper presents two architectures for floating point (FP) adders, which operates in multi-
mode configuration with multi-precision support. First architecture (named QPdDP) works in …
mode configuration with multi-precision support. First architecture (named QPdDP) works in …