Efficient modelling of random access memory cell: An approach using QCA nanocomputing

AN Bahar, A Khan - Turkish Journal of Electrical Engineering …, 2023 - journals.tubitak.gov.tr
Quantum-dot cellular automata (QCA) is innovative and potentially fruitful nanotechnology
that provides a solution for transistor-based circuits with enhanced switching frequency …

64× 64 GM-APD array-based readout integrated circuit for 3D imaging applications

J Wu, Z Qian, Y Zhao, X Yu, L Zheng, W Sun - Science China Information …, 2019 - Springer
Using the high sensitivity of the avalanche photodiode (APD) detector operated in the
Geiger-mode (GM), an array readout integrated circuit (ROIC) comprising a two-segment …

SET tolerant dynamic logic

X She, N Li, DO Erstad - IEEE Transactions on Nuclear Science, 2012 - ieeexplore.ieee.org
This paper presents three SET tolerant dynamic logic circuits. The first one uses redundant
PMOS transistors in the precharge circuit and dual redundant pull down networks in the …

Performance Analysis of Full Adder based on Domino Logic Technique

K Kukreti, P Kumar, S Barthwal… - 2021 6th International …, 2021 - ieeexplore.ieee.org
In modern VLSI area efficient devices are most used because most of the devices are
becoming portable. The Domino logic techniqueis often employed in designing the area …

A new low-power CMOS dynamic logic circuit

S Jia, S Lyu, Q Meng, F Wu, H Xu - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
A new design of half pre-charged CMOS dynamic logic circuit is proposed in this paper. By
adding a transmission transistor and a pre-charge transistor along with an optimization of …

Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

P Meher - 2014 - ethesis.nitrkl.ac.in
The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI
design necessitate new digital logic techniques and styles that are at the same time high …

Circuit Techniques on Improving Timing and Noise in Dynamic CMOS

A Vaidyanadeswaran - 2011 - corescholar.libraries.wright.edu
Dynamic CMOS are widely employed in high-performance CMOS chips due to high speed
and less area in comparison with Static CMOS. However, Dynamic CMOS circuits are …

[引用][C] Analysis of Dynamic Logic for SET

M Palinje, B Dutta, A Yadav