Low leakage CNTFET full adders

RP Somineni, YP Sai, SN Leela - 2015 Global Conference on …, 2015 - ieeexplore.ieee.org
As the technology scales down to 32nm or below, the leakage power starts dominating the
total power. Reduction of this leakage problem is the major problem, today's CMOS …

Low-power multimodal switch for leakage reduction and stability improvement in SRAM cell

M Kavitha, T Govindaraj - Arabian Journal for Science and Engineering, 2016 - Springer
Memory block occupies most of the integrated chip area and an improvement in memory cell
performance will enhance the overall system performance. Ever increasing levels of on-chip …

Optimization of Power and Delay in VLSI Circuits using Hybrid Flip-Flop Circuit

GR Krishna, R Lorenzo - 2023 3rd International Conference On …, 2023 - ieeexplore.ieee.org
In this paper a novel master-slave (MS) hybrid flip-flop is proposed using a single-phase
clock. The proposed circuit is designed in CMOS (Complementary Metal Oxide …

Low leakage power gating technique for subnanometer CMOS circuits

K Manickam, G Thangavel - Turkish Journal of Electrical …, 2016 - journals.tubitak.gov.tr
Static power has become the most important factor in the fabrication of integrated circuits.
Power gating techniques minimize leakage currents and help to develop ultra-low-power …

Leakage minimization in CMOS VLSI circuits: a brief review

S Chaudhury, R Lorenzo - Design and Modeling of Low Power VLSI …, 2016 - igi-global.com
Ever increasing demand for portable and battery-operated systems has lead to aggressive
scaling. While technology scaling facilitates faster and high performance devices, at the …

A comparative review on leakage power minimization techniques in SRAM

AP Kumar, R Lorenzo - Low Power Designs in Nanodevices and Circuits … - taylorfrancis.com
The fast progression in technology and growing market for portable devices demand ultra-
low power dissipation for longer battery life. In the present-day context, electronic circuit …

Aplicação de autômatos celulares para simulação de processos de microfabricação.

FB Colombo - 2016 - teses.usp.br
Autômatos celulares e suas variações são atualmente utilizados para simulação de
diversos processos físicos. De especial interesse para o campo de simulação de processos …

[引用][C] Power and Ground Bounce Reduction Techniques for Nanoscale VLSI Systems

M Kavitha - i-Manager's Journal on Circuits & Systems, 2021 - iManager Publications

[引用][C] Power Gating Techniques for Leakage Reduction in CMOS Circuits-A Brief Survey

M Kavitha, T Govindaraj - i-Manager's Journal on Circuits & …, 2015 - iManager Publications