Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes
VB Sreenivasulu, V Narendar - Microelectronics Journal, 2021 - Elsevier
In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …
Vertically-grown TFETs: an extensive analysis
AS Geege, TSA Samuel - Silicon, 2023 - Springer
TFET is an exciting device for ultra-low and low power implementations since it improves
electrical performance while also providing steeper switching ratio. This study encloses with …
electrical performance while also providing steeper switching ratio. This study encloses with …
[HTML][HTML] Real-time prediction of mechanical behaviors of underwater shield tunnel structure using machine learning method based on structural health monitoring data
Predicting the mechanical behaviors of structure and perceiving the anomalies in advance
are essential to ensuring the safe operation of infrastructures in the long run. In addition to …
are essential to ensuring the safe operation of infrastructures in the long run. In addition to …
Investigating the effects of doping gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications
Influence of Gaussian doping in transistor regions, doping gradient step size (σ), interface
trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge …
trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge …
Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET
In this paper, the electrical parameters are evaluated for the variations of temperature in
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …
Theoretical Investigation of Dual-Material Stacked Gate Oxide-Source Dielectric Pocket TFET Based on Interface Trap Charges and Temperature Variations
KK Nigam, Dharmender, VA Tikkiwal… - Journal of Circuits …, 2023 - World Scientific
In this paper, the performance of dual-material stacked gate oxide-source dielectric pocket-
tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed …
tunnel field-effect transistor (DMSGO-SDP-TFET) has been investigated by considering fixed …
Gate-all-around junctionless FET based label-free dielectric/charge modulation detection of SARS-CoV-2 virus
The recent corona outbreak has necessitated the development of a label-free, highly
sensitive, fast, accurate, and cost-effective biosensor for the detection of SARS-CoV-2 virus …
sensitive, fast, accurate, and cost-effective biosensor for the detection of SARS-CoV-2 virus …
Ultra Sensitive Label-Free Detection of Biomolecules Using Vertically Extended Drain Double Gate Si₀.₅Ge₀.₅ Source Tunnel FET
KN Priyadarshani, S Singh - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This work reports a vertically extended drain double gate Si 0.5 Ge 0.5 source tunnel FET for
the biomolecules detection using its electrical properties modulation in presence of …
the biomolecules detection using its electrical properties modulation in presence of …
Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor
RG Debnath, S Baishya - Microelectronics Journal, 2022 - Elsevier
A simulation study of the impact of interface traps on the performance of the Epitaxial Layer
Tunnel Field Effect Transistor (ETLTFET) having Si (1-x) Ge x as source material is …
Tunnel Field Effect Transistor (ETLTFET) having Si (1-x) Ge x as source material is …
Analysis of nanoscale digital circuits using novel drain-gate underlap DMG hetero-dielectric TFET
In this paper, the investigation of dual metal double gate (DMG) hetero-dielectric TFET with
drain-gate underlap for nanoscale digital applications is analyzed. Drain-gate underlap …
drain-gate underlap for nanoscale digital applications is analyzed. Drain-gate underlap …