For networks on chips to succeed as the next generation of on-chip interconnect,
researchers must solve the major problems involved in designing, implementing, verifying …

The continuous advances in semiconductor technology enable the integration of increasing
numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches …

Over the past ten years, as integrated circuits became increasingly more complex and
expensive, the industry began to embrace new design and reuse methodologies that are …

Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

Memory requirements of intellectual property components (IP) in contemporary multi-
processor systems-on-chip are increasing. Large high-speed external memories, such as …

A growing number of applications, often with firm or soft real-time requirements, are
integrated on the same System on Chip, in the form of either hardware or software …

This paper gives an overview of state-of-the-art regarding the network-on-chip (NoC)
proposals. NoC paradigm replaces dedicated, design-specific wires with scalable, general …

In this paper, we present an area-efficient, globally asynchronous, locally synchronous
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip:
The Next Generation of System-on-Chip Integration examines the current issues restricting …

Security is gaining increasing relevance in the development of embedded devices. Towards
a secure system at each level of design, this paper addresses security aspects related to …