A survey on techniques for improving Phase Change Memory (PCM) lifetime
M Mohseni, AH Novin - Journal of Systems Architecture, 2023 - Elsevier
ABSTRACT PCMs are Non-Volatile Memories (NVMs) that store data using phase-change
semiconductors, such as silicon-chalcogenide glass. In addition to increased integration …
semiconductors, such as silicon-chalcogenide glass. In addition to increased integration …
Bingo spatial data prefetcher
M Bakhshalipour, M Shakerinava… - … Symposium on High …, 2019 - ieeexplore.ieee.org
Applications extensively use data objects with a regular and fixed layout, which leads to the
recurrence of access patterns over memory regions. Spatial data prefetching techniques …
recurrence of access patterns over memory regions. Spatial data prefetching techniques …
Evaluation of hardware data prefetchers on server processors
M Bakhshalipour, S Tabaeiaghdaei… - ACM Computing …, 2019 - dl.acm.org
Data prefetching, ie, the act of predicting an application's future memory accesses and
fetching those that are not in the on-chip caches, is a well-known and widely used approach …
fetching those that are not in the on-chip caches, is a well-known and widely used approach …
Corf: Coalescing operand register file for gpus
The Register File (RF) in GPUs is a critical structure that maintains the state for thousands of
threads that support the GPU processing model. The RF organization substantially affects …
threads that support the GPU processing model. The RF organization substantially affects …
Divide and conquer frontend bottleneck
A Ansari, P Lotfi-Kamran… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
The frontend stalls caused by instruction and BTB misses are a significant source of
performance degradation in server processors. Prefetchers are commonly employed to …
performance degradation in server processors. Prefetchers are commonly employed to …
[PDF][PDF] Multi-lookahead offset prefetching
M Shakerinava… - The Third Data …, 2019 - dpc3.compas.cs.stonybrook.edu
Offset prefetching has been recently proposed as a lowoverhead yet high-performance
approach to eliminate data cache misses or reduce their negative effect. In offset …
approach to eliminate data cache misses or reduce their negative effect. In offset …
BOW: Breathing operand windows to exploit bypassing in GPUs
The Register File (RF) is a critical structure in Graphics Processing Units (GPUs) responsible
for a large portion of the area and power. To simplify the architecture of the RF, it is …
for a large portion of the area and power. To simplify the architecture of the RF, it is …
A survey on pcm lifetime enhancement schemes
Phase Change Memory (PCM) is an emerging memory technology that has the capability to
address the growing demand for memory capacity and bridge the gap between the main …
address the growing demand for memory capacity and bridge the gap between the main …
A congestion-aware routing algorithm for mesh-based platform networks-on-chip
In this paper we propose a new congestion-aware routing algorithm. At the First step, this
algorithm splits NoC into a number of subnets. Then a global routing algorithm within each …
algorithm splits NoC into a number of subnets. Then a global routing algorithm within each …
Energy-efficient permanent fault tolerance in hard real-time systems
FS Mireshghallah, M Bakhshalipour… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
Triple Modular Redundancy (TMR) is a historical and long-time-used approach for masking
various kinds of faults. By employing redundancy and analyzing the results of three separate …
various kinds of faults. By employing redundancy and analyzing the results of three separate …