Many suspensions, many problems: a review of self-suspending tasks in real-time systems

JJ Chen, G Nelissen, WH Huang, M Yang… - Real-Time …, 2019 - Springer
In general computing systems, a job (process/task) may suspend itself whilst it is waiting for
some activity to complete, eg, an accelerator to return data. In real-time systems, such self …

[图书][B] Hard real-time computing systems

GC Buttazzo, G Buttanzo - 1997 - Springer
Real-time computing plays a crucial role in our society since an increasing number of
complex systems rely, in part or completely, on computer control. Examples of applications …

High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks

RS Molina, V Gil-Costa, ML Crespo, G Ramponi - IEEE Access, 2022 - ieeexplore.ieee.org
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …

A safe, secure, and predictable software architecture for deep learning in safety-critical systems

A Biondi, F Nesti, G Cicero, D Casini… - IEEE Embedded …, 2019 - ieeexplore.ieee.org
In the last decade, deep learning techniques reached human-level performance in several
specific tasks as image recognition, object detection, and adaptive control. For this reason …

Model checking PBFT consensus mechanism in healthcare blockchain network

K Zheng, Y Liu, C Dai, Y Duan… - 2018 9th International …, 2018 - ieeexplore.ieee.org
Now blockchain network is used in many areas such as healthcare, energy trading and so
on. However, the research about how to evaluate the performance of the blockchain network …

Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration

D Casini, P Pazzaglia, A Biondi, M Di Natale - Journal of Systems …, 2022 - Elsevier
Hardware accelerators, such as those based on GPUs and FPGAs, offer an excellent
opportunity to efficiently parallelize functionalities. Recently, modern embedded platforms …

A hardware and software task-scheduling framework based on CPU+ FPGA heterogeneous architecture in edge computing

Z Zhu, J Zhang, J Zhao, J Cao, D Zhao, G Jia… - IEEE …, 2019 - ieeexplore.ieee.org
Real-time performance is the primary requirement for edge computing systems. However,
with the surge in data volume and the growing demand for computing power, a computing …

Is your bus arbiter really fair? restoring fairness in axi interconnects for fpga socs

F Restuccia, M Pagani, A Biondi, M Marinoni… - ACM Transactions on …, 2019 - dl.acm.org
AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data
in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not …

Response-time analysis for non-preemptive periodic moldable gang tasks

G Nelissen, JM i Igual, M Nasri - 34th Euromicro Conference on …, 2022 - research.tue.nl
Gang scheduling has long been adopted by the high-performance computing community as
a way to reduce the synchronization overhead between related threads. It allows for several …

SPHERE: A multi-SoC architecture for next-generation cyber-physical systems based on heterogeneous platforms

A Biondi, D Casini, G Cicero, N Borgioli… - IEEE …, 2021 - ieeexplore.ieee.org
This paper presents SPHERE, a project aimed at the realization of an integrated framework
to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and …