Customized compute acceleration in the datacenter is key to the wider roll-out of
applications based on deep neural network (DNN) inference. In this article, we investigate …

Partial reconfiguration (PR) is a key enabler to the design and development of adaptive
systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs) …

FPGAs have demonstrated substantial performance and energy efficiency advantages for
workloads that fit a stream processing model with direct module-to-module communication …

Partial reconfiguration is remaining the core technique to build adaptive systems-on-chip
(SoCs) for modern FPGA architectures. Current support for reconfiguration management …

Machine learning ensembles combine multiple base models to produce a more accurate
output. They can be applied to a range of machine learning problems, including anomaly …

With applications to become increasingly compute-and data-intensive, requiring more
processing power, many Internet of Things (IoT) platforms in robots, drones, and …

In order to overcome the famous von Neumann bottleneck, FPGAs employ a dataflow model
that processes data through a pipeline of operator modules, akin to an assembly line for …

Despite its presence for more than two decades and its proven benefits in expanding the
space of system design, dynamic partial reconfiguration (DPR) is rarely integrated into …

Autonomous systems increasingly rely on on-board computation to avoid the latency
overheads of offloading to more powerful remote computing. This requires the integration of …

Building and testing software for embedded systems can be challenging with an impact on
delivery time, design reproducibility, and collaboration among project contributors. To …