Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch …
JG Favor, MN Michael - US Patent 12,106,111, 2024 - Google Patents
A prediction unit includes a first predictor that provides an output comprising a hashed fetch
address of a current fetch block in response to an input. The first predictor input comprises a …
address of a current fetch block in response to an input. The first predictor input comprises a …
Prediction unit that provides a fetch block descriptor each clock cycle
JG Favor, MN Michael - US Patent 12,020,032, 2024 - Google Patents
A prediction unit includes a single-cycle predictor (SCP) configured to provide a series of
outputs associated with a respective series of fetch blocks on a first respective series of clock …
outputs associated with a respective series of fetch blocks on a first respective series of clock …
Dynamically foldable and unfoldable instruction fetch pipeline
JG Favor, MN Michael, V Soneji - US Patent 12,014,180, 2024 - Google Patents
A dynamically-foldable instruction fetch pipeline receives a first fetch request that includes a
fetch virtual address and includes first, second and third sub-pipelines that respectively …
fetch virtual address and includes first, second and third sub-pipelines that respectively …
Folded instruction fetch pipeline
JG Favor, MN Michael, V Soneji - US Patent 11,977,893, 2024 - Google Patents
An instruction fetch pipeline includes first, second, and third sub-pipelines that respectively
include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a …
include: a TLB that receives a fetch virtual address, a tag random access memory (RAM) of a …
Branch target buffer miss handling
JG Favor, MN Michael - US Patent 12,118,360, 2024 - Google Patents
A microprocessor that includes a prediction unit (PRU) comprising a branch target buffer
(BTB). Each BTB entry is associated with a fetch block (FBlk)(sequential set of instructions …
(BTB). Each BTB entry is associated with a fetch block (FBlk)(sequential set of instructions …
Branch target buffer that stores predicted set index and predicted way number of instruction cache
JG Favor, MN Michael, V Soneji - US Patent 12,008,375, 2024 - Google Patents
A microprocessor includes a branch target buffer (BTB). Each BTB entry holds a tag based
on at least a portion of a virtual address of a block of instructions previously fetched from a …
on at least a portion of a virtual address of a block of instructions previously fetched from a …