Junctionless transistors: State-of-the-art
A Nowbahari, A Roy, L Marchetti - Electronics, 2020 - mdpi.com
Recent advances in semiconductor technology provide us with the resources to explore
alternative methods for fabricating transistors with the goal of further reducing their sizes to …
alternative methods for fabricating transistors with the goal of further reducing their sizes to …
Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering
NB Bousari, MK Anvarifard, S Haji-Nasiri - AEU-International Journal of …, 2019 - Elsevier
This paper is about the compared performance investigation of various structures of Hetero-
Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate …
Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate …
p-Type trigate junctionless nanosheet MOSFET: analog/RF, linearity, and circuit analysis
BS Vakkalakula, N Vadthiya - … Journal of Solid State Science and …, 2021 - iopscience.iop.org
Abstract Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors
(MOSFETs) are realized as an outstanding structure to obtain better area scaling and power …
(MOSFETs) are realized as an outstanding structure to obtain better area scaling and power …
Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications
In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to
investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer …
investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer …
Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor
A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular
core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to …
core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to …
TCAD-based investigation of double gate JunctionLess transistor for UV photodetector
In this work, TCAD-based investigation of junctionLess (JL) architecture having double gate
(DG) has been performed for visualizing the sensitivity of the device against light intensity …
(DG) has been performed for visualizing the sensitivity of the device against light intensity …
An insight into the DC and analog/RF response of a junctionless vertical super-thin body FET towards high-K gate dielectrics
In this work, the junctionless (JL) feature is incorporated in a newly invented device called
vertical super-thin body (VSTB) FET and a comparative exploration of DC and analog/RF …
vertical super-thin body (VSTB) FET and a comparative exploration of DC and analog/RF …
Analytical model of double gate stacked oxide junctionless transistor considering source/drain depletion effects for CMOS low power applications
This paper proposes a 2-D analytical model developed for Double Gate Junctionless
Transistor with a SiO 2/HfO 2 stacked oxide structure. The model is solved by Poisson's …
Transistor with a SiO 2/HfO 2 stacked oxide structure. The model is solved by Poisson's …
Benefitting from high-κ spacer engineering in balistic triple-gate junctionless FinFET-a full quantum study
NB Bousari, MK Anvarifard, S Haji-Nasiri - Silicon, 2020 - Springer
In this paper, a numerically comprehensive investigation have been performed in order to
propose a high-κ spacer triple-gate junctionless FinFET (HKS TG JL FinFET) in three …
propose a high-κ spacer triple-gate junctionless FinFET (HKS TG JL FinFET) in three …
Dual material gate engineering to reduce DIBL in cylindrical gate all around Si nanowire MOSFET for 7-nm gate length
In this work, drain current ID for 7-nm gate length dual-material (DM) cylindrical gate all
around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are …
around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are …