An efficient implementation of GPU virtualization in high performance clusters
Current high performance clusters are equipped with high bandwidth/low latency networks,
lots of processors and nodes, very fast storage systems, etc. However, due to economical …
lots of processors and nodes, very fast storage systems, etc. However, due to economical …
CU2rCU: Towards the complete rCUDA remote GPU virtualization and sharing solution
GPUs are being increasingly embraced by the high performance computing and
computational communities as an effective way of considerably reducing execution time by …
computational communities as an effective way of considerably reducing execution time by …
The DEEP Project An alternative approach to heterogeneous cluster‐computing in the many‐core era
Homogeneous cluster architectures, which used to dominate high‐performance computing
(HPC), are challenged today by heterogeneous approaches utilizing accelerator or co …
(HPC), are challenged today by heterogeneous approaches utilizing accelerator or co …
Scalable communication architecture for network-attached accelerators
S Neuwirth, D Frey, M Nuessle… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
On the road to Exascale computing, novel communication architectures are required to
overcome the limitations of host-centric accelerators. Typically, accelerator devices require a …
overcome the limitations of host-centric accelerators. Typically, accelerator devices require a …
A resource optimized remote-memory-access architecture for low-latency communication
M Nussle, M Scherer, U Bruning - … International Conference on …, 2009 - ieeexplore.ieee.org
This paper introduces a new highly optimized architecture for remote memory access (RMA).
RMA, using put and get operations, is a one-sided communication function which amongst …
RMA, using put and get operations, is a one-sided communication function which amongst …
Co-processor-based behavior monitoring: Application to the detection of attacks against the system management mode
R Chevalier, M Villatel, D Plaquin, G Hiet - Proceedings of the 33rd …, 2017 - dl.acm.org
Highly privileged software, such as firmware, is an attractive target for attackers. Thus, BIOS
vendors use cryptographic signatures to ensure firmware integrity at boot time …
vendors use cryptographic signatures to ensure firmware integrity at boot time …
On achieving high message rates
Computer systems continue to increase in parallelism in all areas. Stagnating single thread
performance as well as power constraints prevent a reversal of this trend, on the contrary …
performance as well as power constraints prevent a reversal of this trend, on the contrary …
An FPGA-based custom high performance interconnection network
M Nüssle, B Geib, H Fröning… - … Computing and FPGAs, 2009 - ieeexplore.ieee.org
An FPGA-based prototype of a custom high-performance network hardware has been
implemented, integrating both a switch and a network interface in one FPGA. The network …
implemented, integrating both a switch and a network interface in one FPGA. The network …
Interconnect technologies for very large spiking neural networks
T Thommes - 2023 - archiv.ub.uni-heidelberg.de
In the scope of this thesis, a neural event communication architecture has been developed
for use in an accelerated neuromorphic computing system and with a packet-based high …
for use in an accelerated neuromorphic computing system and with a packet-based high …
[HTML][HTML] Accelerating network communication and I/O in scientific high performance computing environments
SM Neuwirth - 2019 - ub.uni-heidelberg.de
High performance computing has become one of the major drivers behind technology
inventions and science discoveries. Originally driven through the increase of operating …
inventions and science discoveries. Originally driven through the increase of operating …