Analysis and design of a high-order discrete-time passive IIR low-pass filter
M Tohidian, I Madadi… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of
filtering through a charge-sharing rotation. Its sampling rate is then multiplied through …
filtering through a charge-sharing rotation. Its sampling rate is then multiplied through …
3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver
M Tohidian, I Madadi… - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
Since the invention of radio, superheterodyne has been the architecture of choice for
receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker …
receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker …
A fully integrated discrete-time superheterodyne receiver
M Tohidian, I Madadi… - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS
integration. As the technology scales and wireless standards become ever more …
integration. As the technology scales and wireless standards become ever more …
A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS
Y Xu, S Leuenberger… - … IEEE Symposium on …, 2016 - ieeexplore.ieee.org
A highly compact low-pass filter (LPF) using self-coupled source follower based biquads is
presented. The biquad cell synthesizes a 2 nd-order low-pass transfer function in a single …
presented. The biquad cell synthesizes a 2 nd-order low-pass transfer function in a single …
A continuous-time digital IIR filter with signal-derived timing and fully agile power consumption
Presented is the first continuous-time (CT) digital infinite impulse response (IIR) filter working
on signal-derived timing in lieu of a clock. We introduce a novel design method which …
on signal-derived timing in lieu of a clock. We introduce a novel design method which …
A 0.65mW 20MHz 5th-order low-pass filter with +28.8dBm IIP3 using source follower coupling
Y Xu, J Muhlestein, UK Moon - 2017 IEEE Custom Integrated …, 2017 - ieeexplore.ieee.org
A highly linear continuous-time low-pass filter (LPF) topology using source follower coupling
is presented with excellent power efficiency. It synthesizes a 3 rd-order low-pass transfer …
is presented with excellent power efficiency. It synthesizes a 3 rd-order low-pass transfer …
A 150 kHz–80 MHz BW discrete-time analog baseband for software-defined-radio receivers using a 5th-order IIR LPF, active FIR and a 10 bit 300 MS/s ADC in 28 nm …
A discrete-time (DT) analog baseband for software-defined-radio (SDR) receivers is
presented. A zero-IF baseband signal at the input of a programmable gm is converted to …
presented. A zero-IF baseband signal at the input of a programmable gm is converted to …
A 0.7-MHz–10-MHz Hybrid Baseband Chain With Improved Passband Flatness for LTE Application
A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm
CMOS process. It has an active area of 0.75 \rmmm^2 and a power consumption of 10.8 mW …
CMOS process. It has an active area of 0.75 \rmmm^2 and a power consumption of 10.8 mW …
A 0.02 mm 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
Y Zhao, PI Mak, RP Martins… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently
as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive …
as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive …
A passive CMOS low-pass filter for high speed and high SNDR applications
A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is
high due to the reduced number of clock phases and switches connected to each capacitor …
high due to the reduced number of clock phases and switches connected to each capacitor …