Survey of turbo, LDPC, and polar decoder ASIC implementations

S Shao, P Hailes, TY Wang, JY Wu… - … Surveys & Tutorials, 2019 - ieeexplore.ieee.org
Channel coding may be viewed as the best-informed and most potent component of cellular
communication systems, which is used for correcting the transmission errors inflicted by …

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

M Kingston Roberts, S Kumari… - International Journal of …, 2021 - Wiley Online Library
Information theory coding is an impressive and most celebrated field of research that has
spawned numerous extremely important solutions to the intractable problems of secure data …

High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule

S Kumawat, R Shrestha, N Daga… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper presents architecture of block-level-parallel layered decoder for irregular LDPC
code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11 …

A reconfigurable LDPC decoder optimized for 802.11 n/ac applications

I Tsatsaragkos, V Paliouras - IEEE Transactions on Very Large …, 2017 - ieeexplore.ieee.org
This paper presents a high data-rate low-density parity-check (LDPC) decoder, suitable for
the 802.11 n/ac (WiFi) standard. The innovative features of the proposed decoder relate to …

A fully parallel LDPC decoder architecture using probabilistic min-sum algorithm for high-throughput applications

CC Cheng, JD Yang, HC Lee… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper presents a normalized probabilistic min-sum algorithm for low-density parity-
check (LDPC) codes, where a probabilistic second minimum value, instead of the true …

Low-complexity tree architecture for finding the first two minima

Y Lee, B Kim, J Jung, IC Park - IEEE Transactions on Circuits …, 2014 - ieeexplore.ieee.org
This brief presents an area-efficient tree architecture for finding the first two minima as well
as the index of the first minimum, which is essential in the design of a low-density parity …

A 520k (18900, 17010) array dispersion LDPC decoder architectures for NAND flash memory

KC Ho, CL Chen, HC Chang - IEEE transactions on very large …, 2015 - ieeexplore.ieee.org
Although Latin square is a well-known algorithm to construct low-density parity-check
(LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and …

Optimization techniques for the efficient implementation of high-rate layered QC-LDPC decoders

HC Lee, MR Li, JK Hu, PC Chou… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be
reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) …

A high-throughput trellis-based layered decoding architecture for non-binary LDPC codes using max-log-QSPA

YL Ueng, KH Liao, HC Chou… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
This paper presents a high-throughput decoder architecture for non-binary low-density parity-
check (LDPC) codes, where the q-ary sum-product algorithm (QSPA) in the log domain is …

A reconfigurable and pipelined architecture for standard-compatible LDPC and polar decoding

S Cao, T Lin, S Zhang, S Xu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
With low-density parity-check (LDPC) codes and polar codes selected as the standard
codes for the fifth generation (5G) enhanced Mobile Broad Band scenario (eMBB), a …