Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective

Comparative analysis of capacitorless DRAM performance according to stacked junctionless gate-all-around structures

J Hwang, I Yun - Solid-State Electronics, 2024 - Elsevier
The characteristic comparison of the capacitor-less DRAMs in the structural form variation is
investigated. Based on the simulation results of the three basic structures, such as circular …
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The Study and Modeling of saturation drain voltage for junctionless FinFET

H Lou, Q Lei, Y Yang, X Lin - Micro and Nanostructures, 2024 - Elsevier
In this work, the mechanism and model of saturation drain voltage (V ds, sat) for Junctionless
FinFET (JLF) are investigated. The V ds, sat of JLF is observed to increase linearly with gate …
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Reconfigurable logic-in-memory circuits with ferroelectric nanosheet field-effect transistors

TT Cheng, JC Li, YX Yang, Q Li, HH Hsu… - Physica …, 2024 - iopscience.iop.org
To accommodate the requirements of small device dimensions and the application of
ferroelectric field-effect transistors (FeFETs) in logic-in-memory circuits, we realize the …
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Impact of S/D Extension Length and Sheet Stacking on Transient Behavior of Nanosheet FETs

S Srivastava, S Doge, S Panwar… - … on Circuits and …, 2024 - ieeexplore.ieee.org
The impact of source/drain extension length (LEXT) and vertical sheet stacking on the
transient response of the inverter, made up of nanosheet FETs, has been investigated. This …
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