Reliability challenges with self-heating and aging in finfet technology

H Amrouch, VM van Santen, O Prakash… - 2019 IEEE 25th …, 2019 - ieeexplore.ieee.org
The introduction of FinFET technology as an effective solution to continue technology
scaling has pushed self-heating effects to the forefront of reliability challenges, especially at …

Bti and hcd degradation in a complete 32× 64 bit sram array–including sense amplifiers and write drivers–under processor activity

VM van Santen, S Thomann… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
For the first time, we present a study of BTI and HCD degradation in a 32× 64 cell SRAM
array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one …

Special session: Machine learning for semiconductor test and reliability

H Amrouch, AB Chowdhury, W Jin… - 2021 IEEE 39th VLSI …, 2021 - ieeexplore.ieee.org
With technology scaling approaching atomic levels, IC test and diagnosis of complex System-
on-Chips (SoCs) become overwhelming challenging. In addition, sustaining the reliability of …

An automated setup for the characterization of time-based degradation effects including the process variability in 40-nm CMOS transistors

X Xhafa, AD Güngördü, D Erol, Y Yavuz… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article reports a test chip design in commercial 40-nm process technology to
characterize the level of time-based degradation in metal-oxide-semiconductor field-effect …

Variability-aware approximate circuit synthesis via genetic optimization

K Balaskas, F Klemme, G Zervakis… - … on Circuits and …, 2022 - ieeexplore.ieee.org
One of the major barriers that CMOS devices face at nanometer scale is increasing
parameter variation due to manufacturing imperfections. Process variations severely inhibit …

Lifetime reliability improvement of nano-scale digital circuits using dual threshold voltage assignment

M Raji, R Mahmoudi, B Ghavami, S Keshavarzi - IEEE Access, 2021 - ieeexplore.ieee.org
In nano-scale CMOS technology, circuit reliability is a growing concern for complicated
digital circuits due to manufacturing process variation and aging effects. In this paper, a …

Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability

T Mohamed, VM van Santen, L Alrahis… - … on Circuits and …, 2024 - ieeexplore.ieee.org
Reliability is one of the key concerns in circuit design. The circuit must be able to tolerate
transistor degradation to sustain reliability against timing failure. Whether a transistor is …

Impact of self-heating on performance, power and reliability in finfet technology

VM van Santen, PR Genssler, O Prakash… - 2020 25th Asia and …, 2020 - ieeexplore.ieee.org
Self-heating is one of the biggest threats to reliability in current and advanced CMOS
technologies like FinFET and Nanowire, respectively. Encapsulating the channel with the …

Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor

H Amrouch, VM van Santen… - 2024 IEEE …, 2024 - ieeexplore.ieee.org
In ever-shrinking technology nodes, where transistor 3D structures become increasingly
confined and their features verge on the atomic scale, the phenomena of aging and self …

[PDF][PDF] Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems.

H Amrouch, M Rapp, S Salamin… - A Journey of Embedded …, 2021 - library.oapen.org
More than a decade ago, the semiconductor technology had entered the so-called nano-
CMOS era, in which the transistor's feature sizes became below 90 nm. Since then, the prior …