FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650° C)
B Sklenard, C Xu, P Batude, B Previtali… - … Integration on Silicon …, 2012 - ieeexplore.ieee.org
In this paper, we demonstrate low junction leakage for devices fabricated at low temperature
(≤ 650° C). This is explained by the reduced channel thickness of our device (6 nm). We …
(≤ 650° C). This is explained by the reduced channel thickness of our device (6 nm). We …
Influence of device architecture on junction leakage in low-temperature process FDSOI MOSFETs
In this paper, we demonstrate low junction leakage for Fully Depleted Silicon On Insulator
(FDSOI) devices fabricated with a low thermal budget (⩽ 650° C), which commonly exhibit …
(FDSOI) devices fabricated with a low thermal budget (⩽ 650° C), which commonly exhibit …
Low temperature junction formation by solid phase epitaxy on thin film devices: Atomistic modeling and experimental achievements
B Sklenard, P Batude, L Pasini… - 2014 International …, 2014 - ieeexplore.ieee.org
In this paper, we address the problem of junction formation with a low temperature
processing (≤ 600° C) through Solid Phase Epitaxial Regrowth. We present the main …
processing (≤ 600° C) through Solid Phase Epitaxial Regrowth. We present the main …
3D Monolithic Integration
Typically, σmonolithic is within a few nanometers, ie, lithographic alignment [3], whereas
σparallel is around 0.5 μm [4]. Thanks to its high alignment precision, 3D monolithic is thus …
σparallel is around 0.5 μm [4]. Thanks to its high alignment precision, 3D monolithic is thus …