A method is provided of generating a plurality of diverse routes from a source to a
destination in a weighted directed graph. Such a method may be used for route planning or …

The present application is related to a commonly assigned, US. patent application entitled
“BUFFER INSER TION WITH ADAPTIVE BLOCKAGE AVOIDANCE,” Ser. No. 10/324,732 …

Buffering is a prevalent interconnect optimization technique to help timing closure and is
often performed after placement. A common buffering approach is to construct a Steiner tree …

A method, system, and computer program product for allocating buffer and wire placement in
an integrated circuit design is provided. In one embodiment, the surface of a integrated …

23 Design Automation Conference, 1986, pp. 708–714. Fang, S. et al., Constrained Via
Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Prob lems, 28." …

Buffer insertion has become an increasingly critical optimization in high performance design.
The problem of finding a delay-optimal buffered Steiner tree has been an active area of …

This paper presents Yasper, a tool for modeling, analyzing and simulating workflow systems,
based on Petri nets. Yasper puts Petri net modeling in the hands of business analysts and …

An integrated circuit is a device that includes many electronic components (eg, transistors,
resistors; diodes etc. These components are often interconnected to form multiple circuit …

A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-
block assembly designs, and other styles of design. In a flow of the invention, the technique …

US7080336B2 - Method and apparatus for computing placement costs - Google Patents
US7080336B2 - Method and apparatus for computing placement costs - Google Patents Method …