Systolic-architecture-based matrix multiplications and its realization for multi-sensor bias estimation algorithms

B Gopala Swamy, U Sripati Acharya, P Srihari… - … , Signal Processing, and …, 2021 - Springer
The accelerators are gaining predominant attention in the HW/SW designs and embedded
designs due to the less power consumption and parallel data processing capabilities …

Design and evaluation of a power-efficient approximate systolic array architecture for matrix multiplication

H Waris, C Wang, W Liu… - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
Matrix multiplication (MM) is a basic operation for many Digital Signal Processing
applications. A Systolic Array (SA) is often considered as one of the most favorable …

Improved matrix multiplier design for high‐speed digital signal processing applications

P Saha, A Banerjee, P Bhattacharyya… - IET circuits, devices & …, 2014 - Wiley Online Library
A transistor level implementation of an improved matrix multiplier for high‐speed digital
signal processing applications based on matrix element transformation and multiplication is …

Anscalable matrix computing unit architecture for FPGA, and SCUMO user design interface

A Abbaszadeh, T Iakymchuk, M Bataller-Mompeán… - Electronics, 2019 - mdpi.com
High dimensional matrix algebra is essential in numerous signal processing and machine
learning algorithms. This work describes a scalable square matrix-computing unit designed …

Flexible matrix of controllers for real time parallel control

P Chaber, A Wojtulewicz - Energies, 2022 - mdpi.com
This work aims to develop a novel system, including software and hardware, to perform
independent control tasks in a genuine parallel manner. Currently, to control processes with …

Implementation of High Speed Matrix Multiplier using Vedic Mathematics on FPGA

SV Mogre, DG Bhalke - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
This paper presents unsigned 2x2 High-Speed matrix multiplier using Virtex 5 ML 507
Evaluation Platform (xc5vfx70t-1ff1136) FPGA. The hierarchical structuring has been used to …

Versatile direct and transpose matrix multiplication with chained operations: An optimized architecture using circulant matrices

T Iakymchuk, A Rosado-Munoz… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
With growing demands in real-time control, classification or prediction, algorithms become
more complex while low power and small size devices are required. Matrix multiplication …

A scalable architecture for accelerating multi-operation and continuous floating-point matrix computing on FPGAs

L Zhang, Y Peng, A Huang, X Hu - IEEE Access, 2020 - ieeexplore.ieee.org
Matrix computing is a basic operational model that was broadly used in science and
engineering applications. In this study, we first propose a novel optimization method to …

High performance reconfigurable pipelined matrix multiplication module designer

S Aslan, C Desmouliers, E Oruklu… - 2010 IEEE International …, 2010 - ieeexplore.ieee.org
Matrix multiplication operations are heavily used in communication systems, video, signal
and image processing applications such as echo cancellation, adaptive beamforming, and …

Configurable systolic matrix multiplication

P Kamranfar, SA Shahabi… - … Conference on VLSI …, 2014 - ieeexplore.ieee.org
Matrix multiplication is an important basic operation that is used in a vast range of
applications like image processing and DSP. The design and implementation of a new …