Design of residue generators and multioperand modular adders using carry-save adders

SJ Piestrak - IEEE Transactions on Computers, 1994 - ieeexplore.ieee.org
Residue generator is an essential building block of encoding/decoding circuitry for
arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In …

An efficient reverse converter for the 4-moduli set {2/sup n/-1, 2/sup n/, 2/sup n/+ 1, 2/sup 2n/+ 1} based on the new Chinese remainder theorem

B Cao, CH Chang, T Srikanthan - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
The inherent properties of carry-free operations, parallelism and fault-tolerance have made
the residue number system a promising candidate for high-speed arithmetic and specialized …

Point-targeted sparseness and ling transforms on parallel prefix adder trees

TD Ene, JE Stine - 2022 IEEE 29th Symposium on Computer …, 2022 - ieeexplore.ieee.org
Rephrasing binary addition as a parallel prefix tree problem allows for the generation of high-
performance architectures with logarithmic delay. Modern literature and implementation …

Residue-to-binary conversion by the" quotient function"

G Dimauro, S Impedovo, R Modugno… - … on Circuits and …, 2003 - ieeexplore.ieee.org
This paper presents the quotient function (QF) of the residue number system (RNS), which
provides the integer value of the argument scaled by a modulus of the RNS. An application …

New algorithms for carry propagation

J Grad, JE Stine - Proceedings of the 15th ACM Great Lakes symposium …, 2005 - dl.acm.org
This paper presents the analysis and implementation of different algorithms for carry
propagation in binary adders. Besides traditional AND-OR-Invert based adders, NAND-type …

Design of a cell library for asynchronous microengines

G Gulati, E Brunvand - Proceedings of the 15th ACM Great Lakes …, 2005 - dl.acm.org
Asynchronous microengines are an attractive alternative to globally synchronous systems
for the realization of high performance programmable controllers. However, because of the …

Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor

MA Breuer, A Majumdar… - Proceedings 1988 IEEE …, 1988 - computer.org
Two pseudo-concurrent fault diagnostic approaches, namely, a roving spare technique and
an inverse residue checking technique, and a testing strategy for processing elements in a …

The POTATO chip architecture: a study in tradeoffs for signal processing chip design

B Sharma, R Jain, MA Breuer, AC Parker… - … on Computer Design …, 1988 - computer.org
The authors describe an example signal-processing design which illustrates partitioning,
performance, cost, and fault-tolerance tradeoffs. They focus on high-performance …

[引用][C] Doctor of Philosophy in Electrical Engineering in the Graduate College of the

J GRAD - 2005 - Illinois Institute of Technology