[图书][B] Robust non-linear control through neuroevolution
FJ Gomez - 2003 - search.proquest.com
Many complex control problems require sophisticated solutions that are not amenable to
traditional controller design. Not only is it difficult to model real world systems, but often it is …
traditional controller design. Not only is it difficult to model real world systems, but often it is …
TAPES—Trace-based architecture performance evaluation with SystemC
T Wild, A Herkersdorf, GY Lee - Design Automation for Embedded …, 2005 - Springer
The design of today's System-on-Chip (SoC) architectures faces many challenges in respect
to the involved complexity and heterogeneity. An early and systematic exploration of …
to the involved complexity and heterogeneity. An early and systematic exploration of …
A novel method for optimal placement of STATCOM in distribution networks using sensitivity analysis by DIgSILENT software
In this paper a new method has been proposed to decide optimal placement and best sizing
of static synchronous compensator (STATCOM). Seeking the best place is performed using …
of static synchronous compensator (STATCOM). Seeking the best place is performed using …
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
T Wild, A Herkersdorf… - Proceedings of the Design …, 2006 - ieeexplore.ieee.org
The ever increasing complexity and heterogeneity of modern system-on-chip (SoC)
architectures make an early and systematic exploration of alternative solutions mandatory …
architectures make an early and systematic exploration of alternative solutions mandatory …
[PDF][PDF] SMART: A Simulator of Massive Architectures and Topologies.
F Petrini, M Vanneschi - Euro-PDS, 1997 - Citeseer
Many important results in the area of computer architecture have been achieved using
simulators. In this paper we present SMART, a simulator of parallel architectures. SMART …
simulators. In this paper we present SMART, a simulator of parallel architectures. SMART …
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses
K Ji, M Ling, L Shi - Microprocessors and Microsystems, 2017 - Elsevier
For cache analytical modeling, the stack distance theory is widely utilized to predict LRU-
cache behaviors. Typically, the stack distance histogram collecting is implemented by …
cache behaviors. Typically, the stack distance histogram collecting is implemented by …
Trace factory: Generating workloads for trace-driven simulation of shared-bus multiprocessors
A major concern with high-performance general-purpose workstations is to speed up the
execution of commands, uniprocess applications, and multiprocess applications with coarse …
execution of commands, uniprocess applications, and multiprocess applications with coarse …
The ChARM tool for tuning embedded systems
CA Prete, M Graziano, F Lazzarini - IEEE Micro, 1997 - ieeexplore.ieee.org
ChARM is a simulation tool for tuning ARM-based embedded systems that include cache
memories. ChARM provides a parametric, trace-driven simulation for tuning system …
memories. ChARM provides a parametric, trace-driven simulation for tuning system …
PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors
In high-performance general-purpose workstations and servers, the workload can be
typically constituted of both sequential and parallel applications. Shared-bus shared …
typically constituted of both sequential and parallel applications. Shared-bus shared …
An easy-to-use approach for practical bus-based system design
CH Chen, FF Lin - IEEE Transactions on Computers, 1999 - ieeexplore.ieee.org
We present an easy-to-use model that addresses the practical issues in designing bus-
based shared-memory multiprocessor systems. The model relates the shared-bus width, bus …
based shared-memory multiprocessor systems. The model relates the shared-bus width, bus …