Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance

M She, TJ King - IEEE Transactions on Electron Devices, 2003 - ieeexplore.ieee.org
The write/erase characteristics of Germanium nanocrystal memory device are modeled
using single-charge tunneling theory with quantum confinement and Coulomb blockade …

Nonvolatile memory device using semiconductor nanocrystals and method of forming same

CT Black, KW Guarini - US Patent 7,045,851, 2006 - Google Patents
A floating gate for a field effect transistor (and method for forming the same and method of
forming a uniform nano particle array), includes a plurality of discrete nanoparticles in which …

Electronics below 10 nm

K Likharev - Nano and giga challenges in microelectronics, 2003 - Elsevier
Publisher Summary The aim of this chapter is to review the prospects for the development
and practical introduction of ultra small electron devices, including nanoscale field-effect …

Memory characterization of SiGe quantum dot flash memories with HfO/sub 2/and SiO/sub 2/tunneling dielectrics

DW Kim, T Kim, SK Banerjee - IEEE Transactions on Electron …, 2003 - ieeexplore.ieee.org
In this study, we have developed a SiGe dot floating-gate flash memory with high-K dielectric
(HfO/sub 2/) tunneling oxide. Using SiGe dots and HfO/sub 2/tunneling oxide, a low …

[图书][B] Single-electron devices and circuits in silicon

ZAK Durrani - 2009 - books.google.com
This book reviews research on single-electron devices and circuits in silicon. These devices
provide a means to control electronic charge at the one-electron level and are promising …

Electronic transport in silicon nanocrystals and nanochains

ZAK Durrani, MA Rafiq - Microelectronic Engineering, 2009 - Elsevier
Si nanocrystals and nanochains, prepared by material synthesis, provide a means to define
nanoscale devices using growth rather than lithographic techniques. Electronic transport in …

Room-temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis

E Kapetanakis, P Normand, D Tsoukalas… - Applied physics …, 2002 - pubs.aip.org
We investigated the dependence of implantation dose on the charge storage characteristics
of large-area n-channel metal–oxide–semiconductor field-effect transistors with 1-keV Si+ …

Traps in germanium nanocrystal memory and effect on charge retention: Modeling and experimental measurements

BH Koh, EWH Kan, WK Chim, WK Choi… - Journal of applied …, 2005 - pubs.aip.org
Surface traps, or traps at the interface of the nanocrystal and the surrounding matrix, play an
important role in the charge retention performance of nanocrystal memory transistors. In this …

Sub-20-nm electron devices

K Likharev - Advanced semiconductor and organic nano …, 2003 - Elsevier
Publisher Summary This chapter reviews research and development of ultrasmall electron
devices, including nanoscale field effect transistors (FETs), single-electron transistors …

Device structure for storing charge and method therefore

MA Sadd, S Madhukar, FK Baker - US Patent 6,444,545, 2002 - Google Patents
Silicon nitride layer, in which a plurality of nanoclusters are Sandwiched between oxide
layers. The nanoclusters and the Silicon nitride make up a Storage region, which is particu …