2D materials-based nanoscale tunneling field effect transistors: current developments and future prospects

S Kanungo, G Ahmad, P Sahatiya… - npj 2D Materials and …, 2022 - nature.com
The continuously intensifying demand for high-performance and miniaturized semiconductor
devices has pushed the aggressive downscaling of field-effect transistors (FETs) design …

Operational transconductance amplifier designed with nanowire tunnel-FET with Si, SiGe and Ge sources using experimental data

A de Moraes Nogueira, PG Der Agopian… - Semiconductor …, 2020 - iopscience.iop.org
In this paper operational transconductance amplifiers (OTA) were designed with nanowire
(NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) …

Performance Investigation of Source Extension approach on III-V Vertical Tunnel FET

M Saravanan, E Parthasarathy - IEEE Access, 2024 - ieeexplore.ieee.org
A triple-metal-gate stacked III–V vertical tunnel field-effect transistor (TM-GS-VTFET)
structure is examined. There are two different TM-GS-VTFETs: Device-A, which uses a …

Superior Analog Performance due to Source-Gate Overlap in Vertical Line-Tunneling FETs and Their Circuits

S Hariprasad, SS Dan - Silicon, 2023 - Springer
This paper presents a Vertical Line-Tunneling FET (VLTFET) optimized for superior
performance in analog applications. The saturation mechanism, DC, and small-signal …

Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data

R do Nascimento Tolêdo, W de Lima Silva… - Solid-State …, 2022 - Elsevier
This paper presents the comparison of Low-Dropout Voltage Regulators (LDOs) designed
with Nanowire (NW-TFET) and Line Tunnel FET (Line-TFET), in which the transistors were …

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita, SA Loan, HI Alkhammash… - International Journal of …, 2021 - Wiley Online Library
In this work, we propose and investigate a new pocket‐based Si0. 55Ge0. 45/Si gate normal
tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with …

Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs

AM Nogueira, PGD Agopian, E Simoen… - Solid-State …, 2021 - Elsevier
Abstract An Operational Transconductance Amplifier (OTA) designed with SiGe-source
nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire …

Design of operational transconductance amplifier with Gate-All-Around Nanosheet MOSFET using experimental data from room temperature to 200° C

JCS Sousa, WF Perina, R Rangel, E Simoen… - Solid-State …, 2022 - Elsevier
In this work, a Gate-All-Around Nanosheet transistor (GAA-NSH) is used to design an
operational transconductance amplifier (OTA) operating from room temperature to 200° C. A …

Current mirror designed with GAA nanosheet MOSFETs from room temperature to 200° C

WF Perina, JA Martino, E Simoen… - Semiconductor …, 2021 - iopscience.iop.org
Current mirrors (CMs) are essential building blocks for biasing integrated circuits. The gate-
all-around silicon nanosheet MOSFETs (GAA-NS) are excellent candidates for the sub 7 nm …

Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance

H Simhadri, SS Dan, R Yadav… - International Journal of …, 2021 - Wiley Online Library
This paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device
optimized for superior analog performance. DGLTFET has thrice the on currents I on, at least …